公开(公告)号：US10721568B2

公开(公告)日：2020-07-21

申请号：US16096568

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Georgios C. Dogiamis ,  Feras Eid ,  Adel A. Elsherbini ,  Johanna Swan ,  Shawna M. Liff ,  Thomas L. Sounart ,  Sasha N. Oster

IPC: H04R17/00 ,  B06B1/06

Abstract: Embodiments of the invention include an acoustic transducer device having a base structure that is positioned in proximity to a cavity of an organic substrate, a piezoelectric material in contact with a first electrode of the base structure, and a second electrode in contact with the piezoelectric material. In one example, for a transmit mode, a voltage signal is applied between the first and second electrodes and this causes a stress in the piezoelectric material which causes a stack that is formed with the first electrode, the piezoelectric material, and the second electrode to vibrate and hence the base structure to vibrate and generate acoustic waves.

公开(公告)号：US20200098725A1

公开(公告)日：2020-03-26

申请号：US16143339

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Gerald S. Pasdast ,  Babak Sabi

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: Embodiments herein relate to a semiconductor package or a semiconductor package structure that includes an interposer with opposing first and second sides. A memory and a processing unit may be coupled with the second side of the interposer, and the first side of the interposer may be to couple with the substrate. The processing unit and memory may be communicatively coupled with one another and the substrate by the interposer. Other embodiments may be described or claimed.

公开(公告)号：US20200098692A1

公开(公告)日：2020-03-26

申请号：US16142233

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a bridge structure having a surface; a first die coupled to the surface of the bridge structure by first interconnects, where the first die at least partially overlaps the bridge structure and is non-rectilinear to the bridge structure; and a second die coupled to the surface of the bridge structure by second interconnects, where the second die at least partially overlaps the bridge structure.

公开(公告)号：US20190281717A1

公开(公告)日：2019-09-12

申请号：US16335050

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Son V. Nguyen ,  Rajat Goyal ,  David B. Lampner ,  Dilan Seneviratne ,  Albert S. Lopez ,  Joshua D. Heppner ,  Srinivas V. Pietambaram ,  Shawna M. Liff ,  Nadine L. Dabby

IPC: H05K5/06 ,  H05K5/00 ,  H05K5/02

Abstract: The document discloses a stretchable packaging system for a wearable electronic device. The system includes a first electronic component and a flexible trace connected to the first electronic component. An elastomer layer having a variable thickness at least partially encapsulates the first electronic component and the flexible trace. A first region of the layer has a first thickness that is greater than a second thickness of a second region of the layer that at least partially encapsulates the trace.

公开(公告)号：US20190198961A1

公开(公告)日：2019-06-27

申请号：US16329587

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Georgios C. Dogiamis ,  Telesphor Kamgaing ,  Sasha N. Oster ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Brandon M. Rawlings ,  Richard J. Dischler

IPC: H01P3/16 ,  H01Q9/04 ,  H01P11/00

CPC classification number: H01P3/16 ,  H01P3/122 ,  H01P11/002 ,  H01P11/006 ,  H01Q9/045 ,  H04L67/10

Abstract: A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.

公开(公告)号：US20190189567A1

公开(公告)日：2019-06-20

申请号：US15845990

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Kyle Yazzie ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L21/48 ,  H05K3/10 ,  B29C70/68

CPC classification number: H01L23/562 ,  B29C70/68 ,  B29K2063/00 ,  B29L2031/3481 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49827 ,  H01L23/49838 ,  H05K3/108

Abstract: An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package.

公开(公告)号：US20180337129A1

公开(公告)日：2018-11-22

申请号：US15774937

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Timothy A. Gosselin ,  Yoshihiro Tomita ,  Shawna M. Liff ,  Amram Eitan ,  Mark Saltas

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/48 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/11002 ,  H01L2224/1182 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/14134 ,  H01L2224/14177 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/27002 ,  H01L2224/3201 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/14131 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/27

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

公开(公告)号：US10122089B2

公开(公告)日：2018-11-06

申请号：US15206428

申请日：2016-07-11

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Chuan Hu ,  Shawna M. Liff ,  Larry E. Mosley

IPC: H01Q7/00 ,  H01Q7/06 ,  H01Q1/22 ,  G06F1/16 ,  H01F1/00 ,  H01Q23/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/66 ,  H01L23/31

Abstract: A method apparatus and material are described for radio frequency passives and antennas. In one example, an electronic component has a synthesized magnetic nanocomposite material with aligned magnetic domains, a conductor embedded within the nanocomposite material, and contact pads extending through the nanocomposite material to connect to the conductor.

公开(公告)号：US10068852B2

公开(公告)日：2018-09-04

申请号：US15636117

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Christopher J. Nelson ,  Omkar G. Karhade ,  Feras Eid ,  Nitin A. Deshpande ,  Shawna M. Liff

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/367 ,  H01L23/31

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

公开(公告)号：US20180182736A1

公开(公告)日：2018-06-28

申请号：US15388906

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Feras Eid ,  Nader N. Abazarnia ,  Johanna M. Swan ,  Taesha D. Beasley ,  Sasha N. Oster ,  Tannaz Harirchian ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/29 ,  H01L23/48 ,  H01L23/498 ,  H01L21/56

Abstract: An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein.