公开(公告)号：US11810884B2

公开(公告)日：2023-11-07

申请号：US17570255

申请日：2022-01-06

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L24/25 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L21/568 ,  H01L23/3128 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/255 ,  H01L2224/2512 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US11251150B2

公开(公告)日：2022-02-15

申请号：US17077996

申请日：2020-10-22

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L21/56

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US10508961B2

公开(公告)日：2019-12-17

申请号：US14951422

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Qing Ma ,  Feras Eid ,  Johanna Swan ,  Weng Hong Teh

IPC: G01L9/00 ,  B81B7/00 ,  B81C1/00 ,  H01L23/00 ,  H01L29/84

Abstract: A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity.

公开(公告)号：US10438915B2

公开(公告)日：2019-10-08

申请号：US16239670

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L21/56

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US10179729B2

公开(公告)日：2019-01-15

申请号：US15005826

申请日：2016-01-25

Applicant: INTEL CORPORATION

Inventor： Sarah K. Haney ,  Weng Hong Teh ,  Feras Eid ,  Sasha N. Oster

IPC: B81B7/00 ,  B81C1/00

Abstract: Embodiments of the invention describe hermetic encapsulation for MEMS devices, and processes to create the hermetic encapsulation structure. Embodiments comprise a MEMS substrate stack that further includes a magnet, a first laminate organic dielectric film, a first hermetic coating disposed over the magnet, a second laminate organic dielectric film disposed on the hermetic coating, a MEMS device layer disposed over the magnet, and a plurality of metal interconnects surrounding the MEMS device layer. A hermetic plate is subsequently bonded to the MEMS substrate stack and disposed over the formed MEMS device layer to at least partially form a hermetically encapsulated cavity surrounding the MEMS device layer. In various embodiments, the hermetically encapsulated cavity is further formed from the first hermetic coating, and at least one of the set of metal interconnects, or a second hermetic coating deposited onto the set of metal interconnects.

公开(公告)号：US10156583B2

公开(公告)日：2018-12-18

申请号：US15051856

申请日：2016-02-24

Applicant: Intel Corporation

Inventor： Qing Ma ,  Valluri Rao ,  Feras Eid ,  Kevin Lin ,  Weng Hong Teh ,  Johanna M. Swan ,  Robert L. Sankman

IPC: H01F7/06 ,  G01P15/097 ,  G01P15/105 ,  G01P15/18

Abstract: A method of manufacturing an accelerometer, including placing a magnet on a substrate, laminating a dielectric layer over the magnet, forming a conductive layer over the dielectric layer, the conductive layer including a mass and a conductive path overlying the magnet, removing a portion of the dielectric layer proximate the mass and conductive path such that the mass is movable in response to acceleration of the accelerometer, and forming a dielectric layer over the mass to form a space between the mass and the dielectric layer formed over the mass sufficiently clear such that the mass remains movable.

公开(公告)号：US09674945B2

公开(公告)日：2017-06-06

申请号：US13624288

申请日：2012-09-21

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Kevin Lin ,  Feras Eid ,  Qing Ma

IPC: H01L23/34 ,  H05K1/02 ,  H01L25/00 ,  H05K1/18 ,  H05K3/00

CPC classification number: H05K1/0272 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/0212 ,  H05K1/185 ,  H05K3/0097 ,  H05K2201/097 ,  H05K2203/1536 ,  H05K2203/308 ,  Y10T29/4913

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a microfluidic die to a package structure, wherein the microfluidic die comprises a plurality of asymmetric electrodes that may be coupled with signal pads disposed within the package structure.

公开(公告)号：US09368401B2

公开(公告)日：2016-06-14

申请号：US14501003

申请日：2014-09-29

Applicant: INTEL CORPORATION

Inventor： Weng Hong Teh ,  Vinodhkumar Raghunathan

IPC: H01L23/31 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/2501 ,  H01L2224/73259 ,  H01L2224/821 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

Abstract: Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

Abstract translation: 描述了包括基板及其制造的电子组件。 一个组件包括嵌入在多层基板中的电介质层中的管芯，以及嵌入多层基板中的介电层中的电介质区域。 多层基板包括裸片侧和接地侧，第一介电区和电介质层延伸到管芯侧。 多个通孔位于第一电介质区域内，通孔延伸到管芯侧的焊盘。 描述和要求保护其他实施例。

公开(公告)号：US20160079196A1

公开(公告)日：2016-03-17

申请号：US14922425

申请日：2015-10-26

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/50 ,  H01L25/18

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US09275969B2

公开(公告)日：2016-03-01

申请号：US13717185

申请日：2012-12-17

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna Swan ,  Weng Hong Teh

IPC: H01L27/15 ,  H01L31/12 ,  H01L23/00 ,  H01L25/16 ,  H01S5/022 ,  H01S5/183

CPC classification number: H01S5/02272 ,  H01L21/568 ,  H01L24/18 ,  H01L24/19 ,  H01L25/167 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2924/12042 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02288 ,  H01S5/02292 ,  H01S5/183 ,  H01S5/18305 ,  H01L2924/00

Abstract: This disclosure relates generally to an electronic package that can include a die and a dielectric layer at least partially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the dielectric layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic package different from the first major surface.

Abstract translation: 本公开一般涉及一种电子封装，其可以包括至少部分地包封管芯的管芯和电介质层。 电互连可以电耦合到管芯并且至少部分地通过电介质层。 光发射器可以用电互连的第一个电耦合到管芯，并且被配置为从电子封装的第一主表面发射光。 焊料凸块可以用电互连的第二个电耦合到管芯，并且位于电子封装的不同于第一主表面的第二主表面上。