公开(公告)号：US09312140B2

公开(公告)日：2016-04-12

申请号：US14281166

申请日：2014-05-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Thomas J. Hartswick ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

IPC: H01L21/768 ,  H01L21/78 ,  H01L21/288 ,  H01L23/532 ,  H01L23/58

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US20160071796A1

公开(公告)日：2016-03-10

申请号：US14945854

申请日：2015-11-19

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L29/16 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

公开(公告)号：US08975531B2

公开(公告)日：2015-03-10

申请号：US13746627

申请日：2013-01-22

Applicant: International Business Machines Corporation

Inventor： Felix Anderson ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/40

CPC classification number: H05K1/11 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H05K3/40 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Various embodiments include interconnect structures and methods of forming such structures. The interconnect structures can include a composite copper wire which includes at least two distinct copper sections. The uppermost copper section can have a thickness of approximately 1 micrometer or less, which inhibits surface roughening in that uppermost section, and helps to enhance cap adhesion with overlying layers.

Abstract translation: 各种实施例包括形成这种结构的互连结构和方法。 互连结构可以包括复合铜线，其包括至少两个不同的铜部分。 最上面的铜部分可以具有大约1微米或更小的厚度，这抑制了在最上面的部分的表面粗糙化，并且有助于增强与上覆层的盖子粘附。

公开(公告)号：US20140035169A1

公开(公告)日：2014-02-06

申请号：US14027773

申请日：2013-09-16

Applicant: International Business Machines Corporation

Inventor： Gregory S. Chrisman ,  Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Thomas L. McDevitt ,  Eva A. Shah

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/5227 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire.

Abstract translation: 一种用于制造提供在上表面具有第一高度的金属线的结构的结构和方法。 围绕所述金属线的绝缘材料被蚀刻到所述上表面的所述第一高度以下的第二高度。 在蚀刻所述绝缘材料之后，来自所述上表面的金属线被平坦化以从所述金属线的横向边缘部分去除足够的材料，使得所述侧边缘部分的高度等于围绕所述绝缘材料的所述绝缘材料的所述第二高度 金属丝。

公开(公告)号：US09691623B2

公开(公告)日：2017-06-27

申请号：US15178893

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Thomas J. Hartswick ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

IPC: H01L23/58 ,  H01L21/288 ,  H01L21/768 ,  H01L21/78 ,  H01L23/522 ,  H01L23/00 ,  H01L23/485 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/285 ,  H01L23/528 ,  C25D7/12 ,  C25D3/38 ,  C25D5/10

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US09620371B2

公开(公告)日：2017-04-11

申请号：US14832021

申请日：2015-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Thomas J. Hartswick ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

IPC: H01L21/78 ,  H01L21/768 ,  H01L23/58 ,  H01L21/288 ,  H01L23/522 ,  H01L23/485 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/285 ,  H01L23/528 ,  C25D7/12 ,  C25D3/38 ,  C25D5/10

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US09355972B2

公开(公告)日：2016-05-31

申请号：US14196137

申请日：2014-03-04

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/66 ,  H01L49/02 ,  H01L29/06 ,  H01L23/522 ,  H01L21/762

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Abstract translation: 在混合信号集成电路（IC）的体硅（Si）衬底中制造电介质区域的结构和方法提供了高Q无源谐振器。 通过湿法蚀刻在<100>方向内的本体Si衬底内的深沟槽扩大以形成连续的空腔，其由Si氧化物填充以形成电介质区域。 电介质区域增强了在混合信号IC的金属化层中形成的覆盖无源谐振器的质量（Q）。

公开(公告)号：US09287345B2

公开(公告)日：2016-03-15

申请号：US14013409

申请日：2013-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee ,  John C. Malinowski ,  Anthony K. Stamper

IPC: H01L49/02 ,  H01C7/00 ,  H01C17/075 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L28/20 ,  H01C7/006 ,  H01C17/075 ,  H01L21/7685 ,  H01L23/5228 ,  H01L23/53295 ,  H01L24/11 ,  H01L28/24 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05181 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.

Abstract translation: 公开了同时形成薄膜电阻器和端子接合焊盘的方法。 一种方法包括在端子线上同时形成端子接合焊盘和在另外两条导线上形成薄膜电阻器。

公开(公告)号：US09159671B2

公开(公告)日：2015-10-13

申请号：US14083929

申请日：2013-11-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Trevor A. Thompson ,  Eric J. White

IPC: H01L21/4763 ,  H01L23/498 ,  H01L21/445 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

Abstract translation: 提供了在集成电路中制造铜线的方法。 制造半导体结构的方法包括在掩模中形成线开口。 该方法还包括在导线开口中电镀导电材料。 该方法还包括在导电材料上形成盖层。 该方法还包括去除掩模。 该方法还包括在导电材料的侧面上形成间隔物。 该方法还包括在盖层和侧壁间隔物的表面上形成电介质膜。

公开(公告)号：US20150262911A1

公开(公告)日：2015-09-17

申请号：US14211479

申请日：2014-03-14

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Charles W. Griffin ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC: H01L23/48 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/306

CPC classification number: H01L23/481 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/76898 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372

Abstract: A through silicon via (TSV), method and 3D integrated circuit are disclosed. The TSV extends through a substrate to a back side of the substrate and includes a body including a first metal for coupling to an interconnect on a front side of the substrate. A dielectric collar insulates the body from the substrate. The TSV also includes an end cap coupled to the body on the back side of the substrate, the end cap including a second metal that is different than the first metal. The end cap acts as a grinding stop indicator during back side grinding for 3D integration processing, preventing damage to the dielectric collar and first metal (e.g., copper) contamination of the substrate.

Abstract translation: 公开了一种硅通孔（TSV），方法和3D集成电路。 TSV通过衬底延伸到衬底的背面，并且包括主体，该主体包括用于耦合到衬底的前侧上的互连的第一金属。 电介质套管使主体与衬底绝缘。 TSV还包括在基板背面连接到主体的端帽，端盖包括与第一金属不同的第二金属。 在用于3D一体化处理的后侧研磨期间，端盖用作研磨停止指示器，防止损坏介质套环和衬底的第一金属（例如铜）污染。