公开(公告)号：US20230387027A1

公开(公告)日：2023-11-30

申请号：US17752941

申请日：2022-05-25

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas V. Pietambaram ,  Haobo Chen

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L23/3128 ,  H01L24/16 ,  H01L25/0655 ,  H01L2221/68359 ,  H01L2224/16227

Abstract: A via structure for an embedded component and method for making same. The via structure includes a pillar of conductive material perpendicularly attached to a surface of a build-up dielectric layer. The surface and the pillar are conformally covered by a film layer. The film layer is conformally applied and retains a feature landscape profile. A dielectric layer is located on the film layer, the dielectric layer has an upper dielectric surface that is planar. The pillar has a top that is exposed at the upper dielectric surface. The film layer can act as a barrier to cracking because it is selected to have a higher hardness than the material making up the dielectric layer

公开(公告)号：US20230197661A1

公开(公告)日：2023-06-22

申请号：US17555401

申请日：2021-12-18

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Bai Nie ,  Haobo Chen ,  Jason M. Gamba

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L24/05 ,  H01L2224/0557 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2924/2075 ,  H01L2224/215 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2225/06513

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a first material layer on the first surface of the first die, the first material layer including silicon and nitrogen; a second material layer on the first material layer, the second material layer including a photoimageable dielectric; conductive vias through the first and second material layers, wherein respective ones of the conductive vias are electrically coupled to respective ones of the second conductive contacts on the first die; and a second die in a second layer, wherein the second layer on the first layer, and wherein the second die is electrically coupled to the second conductive contacts on the first die by the conductive vias.

公开(公告)号：US20210375746A1

公开(公告)日：2021-12-02

申请号：US16884452

申请日：2020-05-27

Applicant: INTEL CORPORATION

Inventor： Hongxia Feng ,  Jeremy Ecton ,  Aleksandar Aleksov ,  Haobo Chen ,  Xiaoying Guo ,  Brandon C. Marin ,  Zhiguo Qian ,  Daryl Purcell ,  Leonel Arana ,  Matthew Tingey

IPC: H01L23/522 ,  H01L23/66

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

公开(公告)号：US20210287979A1

公开(公告)日：2021-09-16

申请号：US16817309

申请日：2020-03-12

Applicant: Intel Corporation

Inventor： Veronica Aleman Strong ,  Henning Braunisch ,  Hiroki Tanaka ,  Haobo Chen

IPC: H01L23/498

Abstract: Embodiments may relate to a microelectronic package with an interconnect stack that includes a cavity therein. The cavity may include a dielectric material with a dielectric value less than 3.9. The microelectronic package may further include first and second conductive elements in the cavity, with the dielectric material positioned therebetween. Other embodiments may be described or claimed.

公开(公告)号：US20240222345A1

公开(公告)日：2024-07-04

申请号：US18090707

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/5383 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80447 ,  H01L2224/80895

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, a layer of organic dielectric material over the plurality of interconnect layers, copper pads within the layer of organic dielectric material, a first integrated circuit device copper-to-copper bonded with the copper pads, inorganic dielectric material over the layer of organic dielectric material, the inorganic dielectric material embedding the first integrated circuit device, and the inorganic dielectric material extending across a width of the substrate, and a second integrated circuit device coupled with a substrate surface above the inorganic dielectric material. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240222301A1

公开(公告)日：2024-07-04

申请号：US18147497

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Srinivas Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Sairam Agraharam ,  Ashay Dani ,  Eric J. M. Moret ,  Tarek Ibrahim

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L2224/10122 ,  H01L2224/11011 ,  H01L2924/143 ,  H01L2924/186

Abstract: Methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package.

公开(公告)号：US20240222283A1

公开(公告)日：2024-07-04

申请号：US18147487

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Bohan Shan ,  Bai Nie ,  Xiaoxuan Sun ,  Holly Sawyer ,  Tarek Ibrahim ,  Adwait Telang ,  Dingying Xu ,  Leonel Arana ,  Xiaoying Guo ,  Ashay Dani ,  Sairam Agraharam ,  Haobo Chen ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Methods and apparatus to prevent over-etch in semiconductor packages are disclosed. A disclosed example semiconductor package includes at least one dielectric layer, an interconnect extending at least partially through or from the at least one dielectric layer, and a material on at least a portion of the interconnect, wherein the material comprises at least one of silicon or titanium.

公开(公告)号：US20240222259A1

公开(公告)日：2024-07-04

申请号：US18147535

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Xiyu Hu ,  Rhonda Jack ,  Catherine Mau ,  Hongxia Feng ,  Xiao Liu ,  Wei Wei ,  Srinivas Pietambaram ,  Gang Duan ,  Xiaoying Guo ,  Dingying Xu ,  Kyle Arrington ,  Ziyin Lin ,  Hiroki Tanaka ,  Leonel Arana

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/49894 ,  H01L21/481 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/16

Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit (IC) packages having silicon nitride adhesion promoters are disclosed. An example IC package disclosed herein includes a metal layer on a substrate, a layer on the metal layer, the layer including silicon and nitrogen, and solder resist on the layer.

公开(公告)号：US20240222136A1

公开(公告)日：2024-07-04

申请号：US18091188

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ashay A. Dani ,  Yiqun Bai ,  Dingying Xu ,  Bai Nie ,  Kyle Jordan Arrington ,  Wei Wei ,  Ziyin Lin

IPC: H01L21/321 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/7684

Abstract: Mechanical or chemical processes can form roughened surfaces which can be used for coupling layers of electrical systems such as when forming dies, substrates, computer chips or the like that, when subjected to high stress, are robust enough to remain coupled together.

公开(公告)号：US20240219659A1

公开(公告)日：2024-07-04

申请号：US18089871

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Yiqun Bai ,  Bohan Shan ,  Kyle Jordan Arrington ,  Haobo Chen ,  Dingying Xu ,  Robert Alan May ,  Gang Duan ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4239 ,  H01Q1/2283

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.