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    VERTICAL SOI TRENCH SONOS CELL
    31.
    发明申请
    VERTICAL SOI TRENCH SONOS CELL 有权
    垂直SOI TRENCH SONOS电池

    公开(公告)号：US20090224308A1

    公开(公告)日：2009-09-10

    申请号：US12410935

    申请日：2009-03-25

    申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

    摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    摘要翻译： 提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取 基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

    Resist formulation which minimizes blistering during etching
    32.
    发明授权
    Resist formulation which minimizes blistering during etching 失效
    抗蚀剂制剂，其最小化蚀刻期间的起泡

    公开(公告)号：US06207353B1

    公开(公告)日：2001-03-27

    申请号：US08987808

    申请日：1997-12-10

    申请人： Michael D. Armacost ,  Willard E. Conley ,  Tina J. Cotler-Wagner ,  Ronald A. DellaGuardia ,  David M. Dobuzinsky ,  Michael L. Passow ,  William C. Wille

    发明人： Michael D. Armacost ,  Willard E. Conley ,  Tina J. Cotler-Wagner ,  Ronald A. DellaGuardia ,  David M. Dobuzinsky ,  Michael L. Passow ,  William C. Wille

    IPC分类号： G03F700

    CPC分类号： H01L21/0274 ,  G03F7/039 ,  H01L21/31116 ,  H01L21/31144

    摘要： A resist formulation minimizes blistering during reactive ion etching processes resulting in an increased amount of polymer by-product deposition. Such processes involve exciting a gaseous fluorocarbon etchant with sufficient energy to form a high-density plasma, and the use of an etchant having a carbon-to-fluorine ratio of at least 0.33. In addition to a conventional photoactive component, resists which minimize blistering under these conditions include a resin binder which is a terpolymer having: (a) units that contain acid-labile groups; (b) units that are free of reactive groups and hydroxyl groups; and (c) units that contribute to aqueous developability of the photoresist. After the photoresist is patterned on the silicon oxide layer and the high-density plasma is formed, the high-density plasma is introduced to the silicon oxide layer to etch at least one opening in the silicon oxide layer. Preferably, the terpolymer is made up of about 70% 4-hydroxystyrene, about 20% styrene, and about 10% t-butylacrylate.

    摘要翻译： 抗蚀剂制剂使反应离子蚀刻过程中的起泡最小化，导致聚合物副产物沉积量增加。 这种方法包括以足够的能量激发气态碳氟化合物蚀刻剂以形成高密度等离子体，以及使用碳 - 氟比至少为0.33的蚀刻剂。 除了常规的光活性组分之外，在这些条件下使泡沫最小化的抗蚀剂包括具有以下三元共聚物的树脂粘合剂：（a）含有酸不稳定基团的单元; （b）不含反应性基团和羟基的单元; 和（c）有助于光致抗蚀剂的水性显影性的单元。 在氧化硅层上形成光致抗蚀剂并形成高密度等离子体之后，将高密度等离子体引入到氧化硅层中以蚀刻氧化硅层中的至少一个开口。 优选地，三元共聚物由约70％的4-羟基苯乙烯，约20％的苯乙烯和约10％的丙烯酸叔丁酯组成。

    Method and apparatus for preventing formation of black silicon on edges of wafers
    34.
    发明授权
    Method and apparatus for preventing formation of black silicon on edges of wafers 有权
    防止在硅片边缘形成黑色硅的方法和装置

    公开(公告)号：US06066570A

    公开(公告)日：2000-05-23

    申请号：US209413

    申请日：1998-12-10

    申请人： Dung-Ching Perng ,  David M. Dobuzinsky ,  Ting Hao Wang ,  Klaus Roithner

    发明人： Dung-Ching Perng ,  David M. Dobuzinsky ,  Ting Hao Wang ,  Klaus Roithner

    IPC分类号： H01L21/302 ,  H01L21/20 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/316 ,  H01L21/00

    CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31612

    摘要： A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.

    摘要翻译： 根据本发明的通过减少黑硅沉积来提高芯片产量的方法包括以下步骤：提供适于制造半导体芯片的硅晶片，在晶片的整个表面上沉积第一层，去除第一层的一部分 以暴露适于形成半导体器件的区域并蚀刻晶片，使得第一层的剩余部分防止蚀刻材料在晶片上的再沉积。 一种用于减少黑色硅沉积的半导体组件，包括适于制造半导体芯片的硅晶片，该晶片具有用于形成半导体器件的前表面，后表面和边缘。 在晶片上形成用于覆盖背面和边缘的沉积层，从而防止在蚀刻期间在背面和晶片边缘上再沉积硅。

    Vertical SOI trench SONOS cell
    39.
    发明授权
    Vertical SOI trench SONOS cell 有权
    垂直SOI沟槽SONOS单元

    公开(公告)号：US07893485B2

    公开(公告)日：2011-02-22

    申请号：US11955913

    申请日：2007-12-13

    申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

    摘要： A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    摘要翻译： 提供半导体存储器件和包括体现在机器可读介质中的半导体存储器件的设计结构。 特别地，本发明包括其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体 - 氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元的半导体存储器件，其允许将 基于SOI的互补金属氧化物半导体（CMOS）技术中的致密非易失性随机存取存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

    SEMICONDUCTOR ETCHING METHODS
    40.
    发明申请
    SEMICONDUCTOR ETCHING METHODS 审中-公开
    半导体蚀刻方法

    公开(公告)号：US20090047791A1

    公开(公告)日：2009-02-19

    申请号：US11839681

    申请日：2007-08-16

    申请人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Munir D. Naeem ,  William C. Wille ,  Richard S. Wise

    发明人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Munir D. Naeem ,  William C. Wille ,  Richard S. Wise

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3081 ,  H01L27/10844 ,  H01L27/11

    摘要： A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.

    摘要翻译： 公开了蚀刻半导体结构的方法。 该方法可以包括蚀刻半导体器件的SRAM部分，该方法包括：提供硅衬底层，其上的氮化物层，氮化物层上的光学色散层和其上的硅抗反射涂层; 使用图像层蚀刻硅抗反射涂层; 去除图像层; 在去除硅抗反射涂层的同时蚀刻光学色散层; 同时蚀刻光学色散层和氮化物层; 并同时蚀刻光学色散层，氮化物层和硅衬底。