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69 条记录 (耗时 0.027 秒)

    Signal processing apparatus
    31.
    发明授权
    Signal processing apparatus 失效
    信号处理装置

    公开(公告)号：US5926583A

    公开(公告)日：1999-07-20

    申请号：US731161

    申请日：1996-10-10

    申请人： Seiichiro Iwase ,  Masuyoshi Kurokawa ,  Takao Yamazaki ,  Mitsuharu Ohki

    发明人： Seiichiro Iwase ,  Masuyoshi Kurokawa ,  Takao Yamazaki ,  Mitsuharu Ohki

    IPC分类号： G06T1/20 ,  G06F15/80 ,  G06F17/10 ,  H04N5/14 ,  H04N5/46 ,  H04N5/926 ,  H04N11/00 ,  G06K9/40 ,  G06K9/54 ,  H04N1/40 ,  H04N7/12

    CPC分类号： H04N5/14 ,  G06F17/10 ,  H04N5/926 ,  H04N11/002 ,  H04N5/46

    摘要： A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and an output of any of the processor blocks is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.

    摘要翻译： 具有以一维阵列排列的大量位处理处理器元件的多并行数字信号处理器被视为处理器块，并且多个处理器块依次连接，同时去除冗余，以形成处理器块列 。 多个处理器块被依次连接，使得在后一级的处理器块被提供在先前阶段的处理器块的输出或者与输入数据一起提供，并且任何处理器块的输出作为最终的 输出，从而可以实现具有高性能，多功能性和简单配置的信号处理装置。

    Parallel processor
    32.
    发明授权
    Parallel processor 失效
    并行处理器

    公开(公告)号：US5689450A

    公开(公告)日：1997-11-18

    申请号：US520175

    申请日：1995-08-28

    申请人： Masuyoshi Kurokawa ,  Takao Yamazaki

    发明人： Masuyoshi Kurokawa ,  Takao Yamazaki

    IPC分类号： G06F7/00 ,  G06F15/80 ,  G06T1/20 ,  G06F7/38

    CPC分类号： G06T1/20 ,  G06F15/8015

    摘要： A parallel processor for processing a plurality of pieces of data includes a number of unitary processing units provided in parallel equal to the number of pieces of data. Each of the unitary processing units includes a memory circuit connected to a processing element which exchanges data with two adjoining unitary processing units. Each of the processing elements includes a full adder, a logical operation circuit for performing a logical operation on two inputs connected to a first input of the full adder and a plurality of selector circuits. A first selector circuit selects first data from memory circuits of the unitary processing unit and an adjoining unitary processing unit. A second selector circuit selects second data from memory circuits of the unitary processing unit and an adjoining unitary processing unit. A third selector circuit selects the second data selected by the second selector circuit as a first input to the logical operation circuit. A fourth selector circuit selects the first data selected by the first selector circuit as a second input to the logical operation circuit. A fifth selector circuit selects the second data selected by the second selector circuit as a second input to the full adder. A sixth selector circuit selects the carrier output of the full adder as a third input to the full adder.

    摘要翻译： 用于处理多条数据的并行处理器包括并行提供的数个等于数据片数的单位处理单元。 每个单一处理单元包括连接到与两个邻接的单一处理单元交换数据的处理元件的存储器电路。 每个处理元件包括全加器，用于对连接到全加器的第一输入的两个输入和多个选择器电路执行逻辑运算的逻辑运算电路。 第一选择器电路从单一处理单元的存储电路和相邻的一体处理单元中选择第一数据。 第二选择器电路从单一处理单元的存储电路和相邻的单一处理单元中选择第二数据。 第三选择器电路选择由第二选择器电路选择的第二数据作为逻辑运算电路的第一输入。 第四选择器电路将由第一选择器电路选择的第一数据选择为逻辑运算电路的第二输入。 第五选择器电路选择由第二选择器电路选择的第二数据作为全加器的第二输入。 第六选择器电路选择全加器的载波输出作为全加器的第三输入。

    Parallel processor apparatus having means for processing signals of different lengths
    33.
    发明授权
    Parallel processor apparatus having means for processing signals of different lengths 失效
    具有用于处理不同长度的信号的装置的并行处理器装置

    公开(公告)号：US5666169A

    公开(公告)日：1997-09-09

    申请号：US519719

    申请日：1995-08-28

    申请人： Mitsuharu Ohki ,  Takao Yamazaki ,  Masuyoshi Kurokawa ,  Akihiko Hashiguchi

    发明人： Mitsuharu Ohki ,  Takao Yamazaki ,  Masuyoshi Kurokawa ,  Akihiko Hashiguchi

    IPC分类号： G06F9/38 ,  G06F15/80 ,  G06T1/20 ,  H04N5/14 ,  H04N7/015 ,  H04N5/46 ,  H04N7/12

    CPC分类号： G06F15/8015 ,  H04N5/14

    摘要： To provide a parallel processor apparatus which can perform processing with a good efficiency on signals comprised of data of different lengths. A parallel processor configured by a serial connection of a first parallel processor and a second parallel processor having n number of individual processors and (m-n) number of individual processors. For signals comprised of data of a length, serving as the unit of processing, of m or less and n or more, these parallel processors are connected and used as a single parallel processor apparatus which performs processing equivalent to that by a conventional parallel processor apparatus. For signals comprised of data of a length of n or less, these parallel processors are independently used to perform pipeline processing and thereby perform two times the amount of processing of that performed by a conventional parallel processor apparatus.

    摘要翻译： 提供一种能够对由不同长度的数据组成的信号具有良好效率的处理的并行处理器装置。 由第一并行处理器和具有n个单独处理器和（m-n个）个别处理器的数量的第一并行处理器和第二并行处理器的串行连接器配置的并行处理器。 对于作为处理单位的长度为m以下且n以上的数据构成的信号，这些并行处理器被连接并用作执行与常规并行处理器装置相同的处理的单个并行处理器装置 。 对于由长度为n以下的数据构成的信号，这些并行处理器独立地用于执行流水线处理，从而执行由常规并行处理器装置执行的处理量的两倍。

    Digital multiplying circuit
    34.
    发明授权
    Digital multiplying circuit 失效
    数字乘法电路

    公开(公告)号：US4706211A

    公开(公告)日：1987-11-10

    申请号：US651155

    申请日：1984-09-17

    申请人： Takao Yamazaki ,  Seiichiro Iwase

    发明人： Takao Yamazaki ,  Seiichiro Iwase

    IPC分类号： G06F7/533 ,  G06F7/507 ,  G06F7/52 ,  G06F7/527 ,  G06F7/53

    CPC分类号： G06F7/5338 ,  G06F2207/3884

    摘要： A digital multiplying circuit in a parallel multiplying circuit which can multiply an input which changes at a high data rate by the pipeline processing. A multiplicand is inputted to this circuit. Partial product signal generating circuits of the number corresponding to only the number of partial product signals which are needed are provided. The partial product signal generating circuits produce the partial product signals in accordance with the state of predetermined bits of a multiplier. Each partial product signal is added, thereby obtaining a multiplication output of the multiplicand. The pipeline processing is performed in the adding operation of each partial product signal. The multiplier and multiplicand are delayed. The predetermined partial product signal generating circuits are arranged immediately before the adders which need the partial product signals, thereby obtaining the partial product. With this digital multiplying circuit, the total number of bits of registers is reduced and the circuit scale is made small.

    摘要翻译： 并行乘法电路中的数字乘法电路，其可以将通过流水线处理以高数据速率变化的输入相乘。 被乘数被输入到该电路。 提供了与仅需要的部分产品信号的数量对应的部分产品信号发生电路。 部分乘积信号发生电路根据乘法器的预定位的状态产生部分乘积信号。 添加每个部分乘积信号，从而获得被乘数的乘法输出。 在每个部分积信号的相加操作中执行流水线处理。 乘数和被乘数被延迟。 预定的部分乘积信号发生电路紧接在需要部分乘积信号的加法器之前，从而获得部分乘积。 利用该数字乘法电路，减少寄存器的总位数，使电路规模变小。

    Digital time base corrector
    35.
    发明授权
    Digital time base corrector 失效
    数字时基校正器

    公开(公告)号：US4677499A

    公开(公告)日：1987-06-30

    申请号：US721658

    申请日：1985-04-10

    申请人： Norihisa Shirota ,  Takao Yamazaki ,  Seiichiro Iwase

    发明人： Norihisa Shirota ,  Takao Yamazaki ,  Seiichiro Iwase

    IPC分类号： G11B20/10 ,  A63F7/02 ,  G11B20/18 ,  H03K5/00 ,  H03K5/13 ,  H04N5/92 ,  H04N5/95 ,  H03K5/14

    CPC分类号： H03K5/131 ,  G11B20/18 ,  H04N5/95 ,  H03K2005/00241

    摘要： There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit. A signal selecting circuit is divided into N first unit selecting circuits and a second unit selecting circuit. M of the output signals of a shift register are inputted to the first unit selecting circuits, by which one of them is selected. The outputs of the N first unit selecting circuits are supplied to the second unit selecting circuit, by which one of them is selected. A pipeline process is performed by inserting a delay circuit to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit. Further, the selecting signal can be made variable for every one clock and a delay circuit is inserted on the output side of a selecting signal forming circuit. With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.

    摘要翻译： 提供了一种数字时基校正器，其中由连续数据时间序列组成的一个块的数字输入信号通过可变延迟电路被转换为包括数据缺少间隔或反之亦然的数字信号。 信号选择电路被分为N个第一单元选择电路和第二单元选择电路。 移位寄存器的输出信号的M被输入到第一单元选择电路，通过它们中的一个被选择。 N个第一单位选择电路的输出被提供给第二单元选择电路，由此选择其中一个。 通过插入延迟电路来执行一个时钟周期时间的信号到第二单元选择电路的输入/输出线中的流水线处理。 此外，可以使选择信号每一个时钟变化，并且在选择信号形成电路的输出侧插入延迟电路。 利用该校正器，可以减小选择器的门延迟的影响，并且可以执行高速数据处理。