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    Video signal processor with triple port memory
    1.
    发明授权
    Video signal processor with triple port memory 失效
    具有三端口存储器的视频信号处理器

    公开(公告)号：US6052705A

    公开(公告)日：2000-04-18

    申请号：US701880

    申请日：1996-08-23

    申请人： Seiichiro Iwase ,  Masuyoshi Kurokawa ,  Takao Yamazaki ,  Mitsuharu Ohki

    发明人： Seiichiro Iwase ,  Masuyoshi Kurokawa ,  Takao Yamazaki ,  Mitsuharu Ohki

    IPC分类号： G06F12/04 ,  G06F7/575 ,  G06F15/80 ,  G09G5/00 ,  G11C11/401 ,  H03H17/02 ,  G06F7/32 ,  G06F7/38

    CPC分类号： G06F7/575 ,  G06F2207/3896

    摘要： A digital video signal processor using parallel processing includes an input serial-access memory having memory cells in which data is inputted into successive ones of the memory cells in response to a programmed-controlled pointer and a three or more port data memory unit for writing-in data read out from the serial-access memory. An arithmetic logic unit responds to stored-program control to read out data from the data memory, perform a program-prescribed arithmetic operation, and write the result of the arithmetic operation back to the data memory. An output serial-access memory is controlled so that the arithmetic result will be outputted under program control in a sequential manner. Operation of the interconnected components is effected by a stored-program control unit connected to the input serial-access memory, the data memory, the arithmetic logic unit, and the output serial-access memory.

    摘要翻译： 使用并行处理的数字视频信号处理器包括具有存储单元的输入串行存取存储器，其中响应于编程控制的指针将数据输入到存储单元的连续存储器单元中，以及三个或更多个端口数据存储单元， 在从串行存取存储器读出的数据中。 算术逻辑单元响应存储程序控制从数据存储器读出数据，执行程序规定的算术运算，并将算术运算结果写回数据存储器。 控制输出串行存取存储器，使得算术结果以顺序方式在程序控制下输出。 互连组件的操作由连接到输入串行存取存储器，数据存储器，算术逻辑单元和输出串行存取存储器的存储程序控制单元来实现。

    Signal processing apparatus
    2.
    发明授权
    Signal processing apparatus 失效
    信号处理装置

    公开(公告)号：US5926583A

    公开(公告)日：1999-07-20

    申请号：US731161

    申请日：1996-10-10

    申请人： Seiichiro Iwase ,  Masuyoshi Kurokawa ,  Takao Yamazaki ,  Mitsuharu Ohki

    发明人： Seiichiro Iwase ,  Masuyoshi Kurokawa ,  Takao Yamazaki ,  Mitsuharu Ohki

    IPC分类号： G06T1/20 ,  G06F15/80 ,  G06F17/10 ,  H04N5/14 ,  H04N5/46 ,  H04N5/926 ,  H04N11/00 ,  G06K9/40 ,  G06K9/54 ,  H04N1/40 ,  H04N7/12

    CPC分类号： H04N5/14 ,  G06F17/10 ,  H04N5/926 ,  H04N11/002 ,  H04N5/46

    摘要： A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and an output of any of the processor blocks is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.

    摘要翻译： 具有以一维阵列排列的大量位处理处理器元件的多并行数字信号处理器被视为处理器块，并且多个处理器块依次连接，同时去除冗余，以形成处理器块列 。 多个处理器块被依次连接，使得在后一级的处理器块被提供在先前阶段的处理器块的输出或者与输入数据一起提供，并且任何处理器块的输出作为最终的 输出，从而可以实现具有高性能，多功能性和简单配置的信号处理装置。

    Digital multiplying circuit
    3.
    发明授权
    Digital multiplying circuit 失效
    数字乘法电路

    公开(公告)号：US4706211A

    公开(公告)日：1987-11-10

    申请号：US651155

    申请日：1984-09-17

    申请人： Takao Yamazaki ,  Seiichiro Iwase

    发明人： Takao Yamazaki ,  Seiichiro Iwase

    IPC分类号： G06F7/533 ,  G06F7/507 ,  G06F7/52 ,  G06F7/527 ,  G06F7/53

    CPC分类号： G06F7/5338 ,  G06F2207/3884

    摘要： A digital multiplying circuit in a parallel multiplying circuit which can multiply an input which changes at a high data rate by the pipeline processing. A multiplicand is inputted to this circuit. Partial product signal generating circuits of the number corresponding to only the number of partial product signals which are needed are provided. The partial product signal generating circuits produce the partial product signals in accordance with the state of predetermined bits of a multiplier. Each partial product signal is added, thereby obtaining a multiplication output of the multiplicand. The pipeline processing is performed in the adding operation of each partial product signal. The multiplier and multiplicand are delayed. The predetermined partial product signal generating circuits are arranged immediately before the adders which need the partial product signals, thereby obtaining the partial product. With this digital multiplying circuit, the total number of bits of registers is reduced and the circuit scale is made small.

    摘要翻译： 并行乘法电路中的数字乘法电路，其可以将通过流水线处理以高数据速率变化的输入相乘。 被乘数被输入到该电路。 提供了与仅需要的部分产品信号的数量对应的部分产品信号发生电路。 部分乘积信号发生电路根据乘法器的预定位的状态产生部分乘积信号。 添加每个部分乘积信号，从而获得被乘数的乘法输出。 在每个部分积信号的相加操作中执行流水线处理。 乘数和被乘数被延迟。 预定的部分乘积信号发生电路紧接在需要部分乘积信号的加法器之前，从而获得部分乘积。 利用该数字乘法电路，减少寄存器的总位数，使电路规模变小。

    Digital time base corrector
    4.
    发明授权
    Digital time base corrector 失效
    数字时基校正器

    公开(公告)号：US4677499A

    公开(公告)日：1987-06-30

    申请号：US721658

    申请日：1985-04-10

    申请人： Norihisa Shirota ,  Takao Yamazaki ,  Seiichiro Iwase

    发明人： Norihisa Shirota ,  Takao Yamazaki ,  Seiichiro Iwase

    IPC分类号： G11B20/10 ,  A63F7/02 ,  G11B20/18 ,  H03K5/00 ,  H03K5/13 ,  H04N5/92 ,  H04N5/95 ,  H03K5/14

    CPC分类号： H03K5/131 ,  G11B20/18 ,  H04N5/95 ,  H03K2005/00241

    摘要： There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit. A signal selecting circuit is divided into N first unit selecting circuits and a second unit selecting circuit. M of the output signals of a shift register are inputted to the first unit selecting circuits, by which one of them is selected. The outputs of the N first unit selecting circuits are supplied to the second unit selecting circuit, by which one of them is selected. A pipeline process is performed by inserting a delay circuit to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit. Further, the selecting signal can be made variable for every one clock and a delay circuit is inserted on the output side of a selecting signal forming circuit. With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.

    摘要翻译： 提供了一种数字时基校正器，其中由连续数据时间序列组成的一个块的数字输入信号通过可变延迟电路被转换为包括数据缺少间隔或反之亦然的数字信号。 信号选择电路被分为N个第一单元选择电路和第二单元选择电路。 移位寄存器的输出信号的M被输入到第一单元选择电路，通过它们中的一个被选择。 N个第一单位选择电路的输出被提供给第二单元选择电路，由此选择其中一个。 通过插入延迟电路来执行一个时钟周期时间的信号到第二单元选择电路的输入/输出线中的流水线处理。 此外，可以使选择信号每一个时钟变化，并且在选择信号形成电路的输出侧插入延迟电路。 利用该校正器，可以减小选择器的门延迟的影响，并且可以执行高速数据处理。

    Signal processing apparatus
    5.
    发明授权
    Signal processing apparatus 失效
    信号处理装置

    公开(公告)号：US06038350A

    公开(公告)日：2000-03-14

    申请号：US228237

    申请日：1999-01-11

    申请人： Seiichiro Iwase ,  Masuyoshi Kurokawa ,  Takao Yamazaki ,  Mitsuharu Ohki

    发明人： Seiichiro Iwase ,  Masuyoshi Kurokawa ,  Takao Yamazaki ,  Mitsuharu Ohki

    IPC分类号： G06T1/20 ,  G06F15/80 ,  G06F17/10 ,  H04N5/14 ,  H04N5/46 ,  H04N5/926 ,  H04N11/00 ,  G06K9/36 ,  G06K9/54 ,  G06K9/60 ,  H04N1/40 ,  H04N7/12

    CPC分类号： H04N5/14 ,  G06F17/10 ,  H04N5/926 ,  H04N11/002 ,  H04N5/46

    摘要： A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and any of outputs of the processor block columns is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.

    摘要翻译： 具有以一维阵列排列的大量位处理处理器元件的多并行数字信号处理器被视为处理器块，并且多个处理器块依次连接，同时去除冗余，以形成处理器块列 。 多个处理器块被依次连接，使得在后一级的处理器块被提供在前一级的处理器块的输出或者与输入数据一起提供，并且处理器块列的任何一个输出作为最终的 输出，从而可以实现具有高性能，多功能性和简单配置的信号处理装置。

    Digital signal processing apparatus and information processing system
    6.
    发明授权
    Digital signal processing apparatus and information processing system 失效
    数字信号处理装置及信息处理系统

    公开(公告)号：US5864706A

    公开(公告)日：1999-01-26

    申请号：US693005

    申请日：1996-08-06

    申请人： Masuyoshi Kurokawa ,  Seiichiro Iwase ,  Takao Yamazaki ,  Kenichiro Nakamura

    发明人： Masuyoshi Kurokawa ,  Seiichiro Iwase ,  Takao Yamazaki ,  Kenichiro Nakamura

    IPC分类号： G06F15/80 ,  G06F15/78 ,  G06F12/00

    CPC分类号： G06F15/7857

    摘要： A digital signal processing apparatus and information processing system provide sufficient arithmetic operation performance to process high rate signals in real time and high programming performance to deal with various applications. A group of processor elements is constituted by individual processor elements each formed by disposing an arithmetic and logic unit on the bit lines of a multiport memory wherein their number is equal to or larger than the number of the data bits in a series of serial data, and the plurality of processor elements constituting the group of processor elements are uniformly controlled by controllers mounted on the same silicon chip. Consequently, the multiport memory functioning as a buffer for input data and the arithmetic and logic unit are closely joined together, so data can be communicated smoothly between them. Since the plurality of processor elements are controlled by a single controller so as to operate as a parallel computer, a digital signal processor with a high processing speed can be implemented.

    摘要翻译： 数字信号处理装置和信息处理系统提供足够的算术运算性能，以实时处理高速率信号和高编程性能来处理各种应用。 一组处理器元件由各个处理器元件构成，每个处理器元件通过在多端口存储器的位线上设置算术和逻辑单元而形成，其中它们的数量等于或大于一系列串行数据中的数据位数， 并且构成处理器元件组的多个处理器元件由安装在同一硅芯片上的控制器均匀地控制。 因此，用作输入数据的缓冲器的多端口存储器和算术和逻辑单元紧密地连接在一起，因此可以在它们之间平滑地传送数据。 由于多个处理器元件由单个控制器控制以便作为并行计算机操作，因此可以实现具有高处理速度的数字信号处理器。

    Digital filter
    7.
    发明授权
    Digital filter 失效
    数字滤波器

    公开(公告)号：US4862403A

    公开(公告)日：1989-08-29

    申请号：US797845

    申请日：1985-11-14

    申请人： Seiichiro Iwase ,  Takao Yamazaki

    发明人： Seiichiro Iwase ,  Takao Yamazaki

    IPC分类号： H04N5/21 ,  H03H17/02 ,  H03H17/06

    CPC分类号： H03H17/0202

    摘要： A digital filter has an input terminal provided with an input digital signal. A delay circuit connected to the input terminal produces a plurality of delayed digital signals each having a different delay time with respect to the input digital signal. A first circuit adds the input digital signal and/or the plurality of delayed digital signals to one or more digital coefficient signals of the same value so as to produce one or more added digital signals. A circuit multiplies the one or more respective digital coefficient signals by the one or more added digital signals and/or one or more of the plurality of delayed digital signals to produce a plurality of multiplied digital signals. A second circuit adds the plurality of multiplied digital signals to produce an output digital signal, and a circuit connected between the delay circuit and a multiplying circuit increases the one or more added digital signals and/or the one or more of the plurality of delayed digital signals by one or more predetermined numbers of times, whereby the one or more respective digital coefficient signals have inversely proportional values corresponding to the one or more predetermined numbers of times of the values of the one or more added digital signals and/or the one or more of the plurality of delayed digital signals.

    摘要翻译： 数字滤波器具有设置有输入数字信号的输入端。 连接到输入端的延迟电路产生多个相对于输入数字信号具有不同延迟时间的延迟数字信号。 第一电路将输入数字信号和/或多个延迟的数字信号添加到相同值的一个或多个数字系数信号，以便产生一个或多个相加的数字信号。 一个电路将一个或多个相应的数字系数信号乘以一个或多个相加的数字信号和/或多个延迟的数字信号中的一个或多个，以产生多个相乘的数字信号。 第二电路将多个相乘的数字信号相加以产生输出数字信号，并且连接在延迟电路和乘法电路之间的电路增加一个或多个相加的数字信号和/或多个延迟数字信号中的一个或多个 一个或多个预定次数的信号，由此一个或多个相应的数字系数信号具有对应于一个或多个相加数字信号的值的一个或多个预定次数的反比例值和/或一个或多个 更多的多个延迟数字信号。