公开(公告)号：US20090081418A1

公开(公告)日：2009-03-26

申请号：US11858615

申请日：2007-09-20

申请人： Robert D. Allen ,  Phillip J. Brock ,  Blake W. Davis ,  Wu-Song S. Huang ,  Qinghuang Lin ,  Alshakim Nelson ,  Sampath Purushothaman ,  Ratnam Sooriyakumaran

发明人： Robert D. Allen ,  Phillip J. Brock ,  Blake W. Davis ,  Wu-Song S. Huang ,  Qinghuang Lin ,  Alshakim Nelson ,  Sampath Purushothaman ,  Ratnam Sooriyakumaran

IPC分类号： B32B5/00 ,  G03F7/00

CPC分类号： H01L21/76808 ,  H01L21/02137 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/0276 ,  H01L21/3122 ,  H01L21/76802 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. In general terms, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating that is located atop a substrate. The inorganic ARC is liquid deposited and comprises a polymer that has at least one monomer unit comprising the formula M-R1 wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La and R1 is a chromophore. At least one interconnect pattern is formed within the at least one patternable low-k material and thereafter the at least one patternable low-k material is cured. The inventive method can be used to form dual-damascene interconnect structures as well as single-damascene interconnect structures.

摘要翻译： 本发明提供一种制造互连结构的方法，其中可图案化的低k材料替代了使用单独的光致抗蚀剂和电介质材料的需要。 具体地说，本发明涉及一种制备具有至少一个可图案化的低k电介质和至少一种无机抗反射涂层的单镶嵌和双镶嵌低k互连结构的简化方法。 通常，提供了一种方法，其包括在位于基底顶部的无机抗反射涂层的表面上提供至少一种可图案化的低k材料。 无机ARC是液体沉积的，并且包含具有至少一个单体单元的聚合物，该单体单元包括式M-R1，其中M是Si，Ge，B，Sn，Fe，Ta，Ti，Ni，Hf和La中的至少一种， R1是发色团。 在至少一个可模制的低k材料内形成至少一个互连图案，此后至少一个可图案化的低k材料固化。 本发明的方法可用于形成双镶嵌互连结构以及单镶嵌互连结构。

公开(公告)号：US20090075472A1

公开(公告)日：2009-03-19

申请号：US11857760

申请日：2007-09-19

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US20080284039A1

公开(公告)日：2008-11-20

申请号：US11750892

申请日：2007-05-18

申请人： Matthew E. Colburn ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

发明人： Matthew E. Colburn ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer dielectric material by a first lithographic process that results in both via features and ternary features being formed in the interconnect structure. The method further includes forming a second pattern within the interlayer dielectric material by a second lithographic process to form line features within the interconnect structure. Hence the method forms the three separate distinct patterned structures using only two lithographic processes for each interconnect level.

摘要翻译： 一种制造互连结构的方法，用于将半导体衬底互连以具有三个不同的图案化结构，使得互连结构既提供低k和高结构完整性。 该方法包括在半导体衬底上沉积层间电介质，通过第一光刻工艺在层间电介质材料内形成第一图案，该第一光刻工艺导致在互连结构中形成通孔特征和三元特征。 该方法还包括通过第二光刻工艺在层间电介质材料内形成第二图案以在互连结构内形成线特征。 因此，该方法仅对每个互连级别仅使用两个光刻工艺形成三个独立的不同图案结构。

公开(公告)号：US20080280416A1

公开(公告)日：2008-11-13

申请号：US12180827

申请日：2008-07-28

申请人： Stephen W. Bedell ,  Keith Edward Fogel ,  Bruce Kenneth Furman ,  Sampath Purushothaman ,  Devendra K. Sadana ,  Anna Wanda Topol

发明人： Stephen W. Bedell ,  Keith Edward Fogel ,  Bruce Kenneth Furman ,  Sampath Purushothaman ,  Devendra K. Sadana ,  Anna Wanda Topol

IPC分类号： H01L21/30 ,  H01L21/822

CPC分类号： H01L21/76259 ,  Y10T428/249961

摘要： Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a three dimensional integrated structure is provided.

摘要翻译： 提供了制造半导体器件的技术。 一方面，提供了层转移结构。 层转移结构包括具有调节孔隙度的多孔区域的载体衬底和在其中限定分离平面的注入物质的组合。 另一方面，提供了一种形成层转移结构的方法。 另一方面，提供一种形成三维一体化结构的方法。

公开(公告)号：US07397691B2

公开(公告)日：2008-07-08

申请号：US11409858

申请日：2006-04-24

申请人： Azeez Bhavnagarwala ,  Stephen V. Kosonocky ,  Sampath Purushothaman ,  Kenneth P. Rodbell

发明人： Azeez Bhavnagarwala ,  Stephen V. Kosonocky ,  Sampath Purushothaman ,  Kenneth P. Rodbell

IPC分类号： G11C11/00

CPC分类号： G11C11/4125 ,  Y10S257/903

摘要： A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.

摘要翻译： 存储单元包括字线，具有第一输入和第一输出的第一数字逆变器以及具有第二输入和第二输出的第二数字反相器。 此外，存储单元还包括将第一输出连接到第二输入的第一反馈连接和将第二输出连接到第一输入的第二反馈连接。 第一反馈连接包括第一电阻元件，第二反馈连接包括第二电阻元件。 更重要的是，每个数字逆变器都有相关的电容。 存储单元被配置为使得读取存储器单元包括将读取电压脉冲施加到字线。 此外，第一和第二电阻元件被配置为使得第一和第二反馈连接具有比施加的读取电压脉冲更长的电阻 - 电容感应延迟。

公开(公告)号：US20080122106A1

公开(公告)日：2008-05-29

申请号：US11518773

申请日：2006-09-11

申请人： Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Poncth

发明人： Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Poncth

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/7682

摘要： A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.

摘要翻译： 在具有转印到电介质层上的图案的电介质层和在图案周围的电介质层上转移的自对准阻挡掩模的衬底上产生气隙的结构和方法。

公开(公告)号：US20080042283A1

公开(公告)日：2008-02-21

申请号：US11857797

申请日：2007-09-19

申请人： Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga Shobha ,  Terry Spooner

发明人： Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga Shobha ,  Terry Spooner

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same in which the critical dimension of the conductive features are not altered by a plasma damaged layer are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modifies the density of the dielectric material such that the treated surfaces become denser than the bulk dielectric not subjected to the treatment. The treatment step is performed prior to deposition of the noble metal liner.

摘要翻译： 提供了一种互连结构及其制造方法，其中导电特征的临界尺寸不被等离子体损伤层改变。 根据本发明，对化学蚀刻介电材料进行处理步骤，该处理步骤改变介电材料的密度，使得处理的表面变得比不经受处理的体电介质更致密。 处理步骤在沉积贵金属衬垫之前进行。

公开(公告)号：US20060264036A1

公开(公告)日：2006-11-23

申请号：US11491816

申请日：2006-07-24

申请人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Tomothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

发明人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Tomothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

摘要翻译： 在多电平微电子集成电路中，空气包括永久线路电介质，超低K材料通过电介质。 在通过清洁热分解除去牺牲材料并通过IC结构中的孔隙率辅助副产物扩散后，将空气供应到线路电平。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气结合到本发明产生的程度，使层内和层间介电值最小化。

公开(公告)号：US20060103023A1

公开(公告)日：2006-05-18

申请号：US10988484

申请日：2004-11-12

申请人： Azeez Bhavnagarwala ,  Stephen Kosonocky ,  Satyanarayana Nitta ,  Sampath Purushothaman

发明人： Azeez Bhavnagarwala ,  Stephen Kosonocky ,  Satyanarayana Nitta ,  Sampath Purushothaman

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76801 ,  G11C11/412 ,  H01L23/53295 ,  H01L27/11 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip is described. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

摘要翻译： 描述了在一组区域中具有比在同一微电子芯片上的其它区域更高的互连电容的混合互连结构。 提供了几种制造这种结构的方法。 描述了这样的混合互连结构的电路实现，其能够增加静态噪声容限并且减少SRAM单元中的泄漏以及用于这种芯片中的SRAM和逻辑的公共电源电压。 还教导了能够将这些电路优点与更高的互连性能速度和优异的机械鲁棒性相结合的方法。

公开(公告)号：US20050272341A1

公开(公告)日：2005-12-08

申请号：US11150059

申请日：2005-06-10

申请人： Matthew Colburn ,  Satyanarayana Nitta ,  Sampath Purushothaman

发明人： Matthew Colburn ,  Satyanarayana Nitta ,  Sampath Purushothaman

IPC分类号： H01J9/14 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a low k, ultra-low k, and extreme-low k multilayer interconnect structure on a substrate in which the interconnect line features are separated laterally by a dielectric with vertically oriented nano-scale voids formed by perforating it using sub-optical lithography patterning and etching techniques and closing off the tops of the perforations by a dielectric deposition step. The lines are supported either by solid or patterned dielectric features underneath. The method avoids the issues associated with the formation of air gaps after the fabrication of conductor patterns and those associated with the integration of conventional low k, ultra-low k and extreme low k dielectrics which have porosity present before the formation of the interconnect patterns.

摘要翻译： 一种用于在衬底上制造低k，超低k和极低k多层互连结构的方法，其中互连线特征由具有垂直取向的纳米级空隙的电介质侧向分开， 光刻图案和蚀刻技术，并通过介电沉积步骤封闭穿孔的顶部。 线路由固体或图案化的电介质特征支撑。 该方法避免了在形成导体图案之后与形成气隙相关的问题，以及与形成互连图案之前具有孔隙率的常规低k，超低k和极低k电介质的集成相关联的问题。