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    THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION
    31.
    发明申请
    THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION 审中-公开

    公开(公告)号：US20170169885A1

    公开(公告)日：2017-06-15

    申请号：US15444982

    申请日：2017-02-28

    Applicant: Micron Technology, Inc.

    Inventor： Qiang Tang ,  Feng Pan ,  Ramin Ghodsi ,  Mark A. Helm

    IPC: G11C11/56

    CPC classification number: G11C11/5642 ,  G11C7/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.

    Data line arrangement and pillar arrangement in apparatuses
    33.
    发明授权
    Data line arrangement and pillar arrangement in apparatuses 有权
    设备中的数据线布置和柱布置

    公开(公告)号：US09159736B2

    公开(公告)日：2015-10-13

    申请号：US14175901

    申请日：2014-02-07

    Applicant: Micron Technology, Inc.

    Inventor： Luyen Vu ,  Mark A. Helm

    IPC: H01L27/115 ,  H01L29/16 ,  H01L29/04

    CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L29/16

    Abstract: Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).

    Abstract translation: 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最紧密的包装布置包括具有7个不同支柱的至少部分的重复支柱图案。 重复柱图案中的相应一个中的每个不同的支柱能够电耦合到多条数据线的不同数据线。 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最接近的包装布置包括具有7个不同柱的至少一部分的重复柱图形。 重复柱状图案的所有7个不同的柱由单个排水侧选择栅（SGD）包围。

    Implementing variable number of bits per cell on storage devices
    34.
    发明授权
    Implementing variable number of bits per cell on storage devices 有权

    公开(公告)号：US12086466B2

    公开(公告)日：2024-09-10

    申请号：US18116526

    申请日：2023-03-02

    Applicant: Micron Technology, Inc.

    Inventor： Mark A. Helm

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0673

    Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations including programming first data to a set of memory cells of a first wordline using a first number of bits per memory cell. Responsive to receiving second data to program to the set of memory cells of the first wordline, the operations further include determining an error rate associated with a second wordline adjacent to the first wordline. Responsive to determining that the error rate satisfies a threshold criterion, the operations further include selecting a second number of bits per memory cell to program the second data to the first wordline and reprograming, using the second number of bits per memory cell, the first wordline storing the first data by programming second data to the set of memory cells while maintaining the first data.

    Status check using chip enable pin
    36.
    发明授权
    Status check using chip enable pin 有权

    公开(公告)号：US11500791B2

    公开(公告)日：2022-11-15

    申请号：US17117933

    申请日：2020-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

    IPC: G06F13/16 ,  G06F1/26

    Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

    IMPLEMENTING FAULT TOLERANT PAGE STRIPES ON LOW DENSITY MEMORY SYSTEMS
    37.
    发明申请
    IMPLEMENTING FAULT TOLERANT PAGE STRIPES ON LOW DENSITY MEMORY SYSTEMS 有权

    公开(公告)号：US20210200461A1

    公开(公告)日：2021-07-01

    申请号：US17079048

    申请日：2020-10-23

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Mark A. Helm ,  Giuseppina Puzzilli ,  Peter Feeley ,  Yifen Liu ,  Violante Moschiano ,  Akira Goda ,  Sampath K. Ratnam

    IPC: G06F3/06

    Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

    Boosted channel programming of memory
    39.
    发明授权
    Boosted channel programming of memory 有权

    公开(公告)号：US09947418B2

    公开(公告)日：2018-04-17

    申请号：US15096439

    申请日：2016-04-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Mark A. Helm ,  Kalyan C. Kavalipurapu

    IPC: G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10

    Abstract: Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.

    BOOSTED CHANNEL PROGRAMMING OF MEMORY
    40.
    发明申请
    BOOSTED CHANNEL PROGRAMMING OF MEMORY 有权

    公开(公告)号：US20170294233A1

    公开(公告)日：2017-10-12

    申请号：US15096439

    申请日：2016-04-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Mark A. Helm ,  Kalyan C. Kavalipurapu

    IPC: G11C16/34 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10

    Abstract: Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.

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