中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

96 records (took 0.025 seconds)

    Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions
    32.
    发明申请
    Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions 有权
    存储阵列，半导体结构和形成半导体结构的方法

    公开(公告)号：US20140017865A1

    公开(公告)日：2014-01-16

    申请号：US14030880

    申请日：2013-09-18

    Applicant: Micron Technology, Inc.

    Inventor： Lars P Heineck ,  Shyam Surthi ,  Jaydip Guha

    IPC: H01L29/66

    CPC classification number: H01L27/10802 ,  H01L21/28132 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/7841

    Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

    Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。 每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。 数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。 一些实施例包括形成存储器阵列的方法。 可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。 基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。 线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

    Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith
    33.
    发明申请
    Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith 有权
    形成垂直晶体管的方法和至少一个导电线电耦合的方法

    公开(公告)号：US20130237023A1

    公开(公告)日：2013-09-12

    申请号：US13869112

    申请日：2013-04-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

    IPC: H01L21/8234

    CPC classification number: H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

    Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

    Abstract translation: 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

    APPARATUS WITH SELF-ALIGNED CONNECTION AND RELATED METHODS
    35.
    发明公开
    APPARATUS WITH SELF-ALIGNED CONNECTION AND RELATED METHODS 审中-公开

    公开(公告)号：US20240194529A1

    公开(公告)日：2024-06-13

    申请号：US18507019

    申请日：2023-11-10

    Applicant: Micron Technology, Inc.

    Inventor： Shyam Surthi ,  David H. Wells

    IPC: H01L21/768 ,  H01L21/033 ,  H01L21/32 ,  H10B69/00

    CPC classification number: H01L21/76897 ,  H01L21/0334 ,  H01L21/32 ,  H01L21/76805 ,  H10B69/00

    Abstract: Semiconductor devices including self-aligned vertical connectors are disclosed herein. The self-aligned vertical connectors may have upper and lower portions that are concentric or have fixed relative positions across the connectors. The concentric or fixed relative positions may be aligned with a corresponding circuit or a bit line based on forming a conformal depression by depositing a controlled amount of conformal layer that fills wells adjacent to the bit line at a target location of the vertical connector. The vertical connector can be formed using the conformal depression, which may be self-aligned relative to the bit line as a result of filling the wells with the controlled amount of the conformal layer.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    37.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20230043163A1

    公开(公告)日：2023-02-09

    申请号：US17395726

    申请日：2021-08-06

    Applicant: Micron Technology, Inc.

    Inventor： Shyam Surthi

    IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

    Abstract: Some embodiments include an integrated assembly having a stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions have first conductive structures, and the proximal regions have second conductive structures. Detectable interfaces are present where the first conductive structures join to the second conductive structures. Some embodiments include methods of forming integrated assemblies.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    38.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20230034157A1

    公开(公告)日：2023-02-02

    申请号：US17389864

    申请日：2021-07-30

    Applicant: Micron Technology, Inc.

    Inventor： Byeung Chul Kim ,  Davide Resnati ,  Gianpietro Carnevale ,  Shyam Surthi

    IPC: H01L27/11582

    Abstract: Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.

Patent Agency Ranking