公开(公告)号：US20170077052A1

公开(公告)日：2017-03-16

申请号：US14853807

申请日：2015-09-14

Applicant: Micron Technology, Inc.

Inventor： Giorgio Mariottini ,  Sameer Vadhavkar ,  Wayne Huang ,  Anilkumar Chandolu ,  Mark Bossler

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/02135 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0361 ,  H01L2224/03906 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05082 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/05687 ,  H01L2224/10145 ,  H01L2224/114 ,  H01L2224/11472 ,  H01L2224/13018 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/3651 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/053

Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

Abstract translation: 本技术涉及制造用于管芯到管芯和/或封装到封装互连及相关系统的凸块下金属（UBM）结构的套圈。 半导体管芯包括具有固态部件的半导体材料和至少部分延伸穿过半导体材料的互连。 在半导体材料之上形成凸块下金属（UBM）结构，并且电耦合到相应的互连。 套环围绕UBM结构的侧表面的至少一部分，并且焊料材料设置在UBM结构的顶表面上。

公开(公告)号：US20250140691A1

公开(公告)日：2025-05-01

申请号：US19008496

申请日：2025-01-02

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  Anilkumar Chandolu

IPC: H01L23/528 ,  G11C16/04 ,  H01L21/768 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprise a channel material extending vertically through the stack. The electronic device comprises an additional stack overlying the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, and pillars extending through the additional stack and overlying the strings of memory cells. Each of the pillars is horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells. The electronic device comprises conductive lines overlying the pillars, and interconnect structures directly contacting the pillars and the conductive lines. Related electronic devices, systems, and methods are also described.

公开(公告)号：US20230403849A1

公开(公告)日：2023-12-14

申请号：US18366748

申请日：2023-08-08

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one slit region divides the stack structure into blocks. Each block comprises an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stack structure. Additional microelectronic devices are also disclosed as are related methods and electronic systems.

公开(公告)号：US11818888B2

公开(公告)日：2023-11-14

申请号：US17822036

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Raja Kumar Varma Manthena ,  Anilkumar Chandolu

IPC: H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.

公开(公告)号：US11723196B2

公开(公告)日：2023-08-08

申请号：US17063101

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L27/11582 ,  H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one slit region divides the stack structure into blocks. Each block comprises an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stack structure. Additional microelectronic devices are also disclosed as are related methods and electronic systems.

公开(公告)号：US11626388B2

公开(公告)日：2023-04-11

申请号：US17580521

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu

IPC: H01L21/76 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/367

Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

公开(公告)号：US11482536B2

公开(公告)日：2022-10-25

申请号：US16937303

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Tom J. John ,  Darwin A. Clampitt ,  Anilkumar Chandolu ,  Prakash Rau Mokhna Rau ,  Christopher J. Larsen ,  Kye Hyun Baek

IPC: H01L27/11582 ,  H01L21/768

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

公开(公告)号：US11387245B2

公开(公告)日：2022-07-12

申请号：US16851638

申请日：2020-04-17

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Christopher J. Larsen ,  Anilkumar Chandolu ,  Wesley O. McKinsey ,  Tom J. John ,  Arun Kumar Dhayalan ,  Prakash Rau Mokhna Rau

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11556

Abstract: An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

公开(公告)号：US20210343624A1

公开(公告)日：2021-11-04

申请号：US17367990

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Chet E. Carter ,  Anilkumar Chandolu ,  Justin B. Dorhout ,  Jun Fang ,  Matthew J. King ,  Brett D. Lowe ,  Matthew Park ,  Justin D. Shepherdson

IPC: H01L23/48 ,  H01L21/033 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519

Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

公开(公告)号：US20210225715A1

公开(公告)日：2021-07-22

申请号：US17207989

申请日：2021-03-22

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Lisa R. Copenspire-Ross ,  Michael D. Kenney

IPC: H01L21/66 ,  G01N21/95 ,  H01L23/00

Abstract: Semiconductor devices having measurement features and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a plurality of stacked semiconductor dies each having measurement features formed along an outer periphery of a surface thereof. One or more image capture devices can image the semiconductor device and a controller can detect the measurement features in imaging data received from the image capture devices. The controller can further determine the distance between two or more of the measurement features to estimate a bond line thickness between semiconductor dies in the stack.