公开(公告)号：US20240096433A1

公开(公告)日：2024-03-21

申请号：US18521382

申请日：2023-11-28

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/20 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/20 ,  G11C29/4401

Abstract: A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group. The operations can also include distributing the write operations to each group according to the share of write operations determined for the group.

公开(公告)号：US20240071483A1

公开(公告)日：2024-02-29

申请号：US17898392

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Francesco Mastroianni ,  Andrea Martinelli ,  Efrem Bolandrina ,  Lucia Di Martino ,  Riccardo Muzzetto ,  Zhongyuan Lu ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G11C11/56 ,  G06F3/06 ,  G06F12/02

CPC classification number: G11C11/5628 ,  G06F3/0679 ,  G06F12/0246

Abstract: Disclosed are techniques for correcting drift accumulation in memory cells. In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.

公开(公告)号：US20230422471A1

公开(公告)日：2023-12-28

申请号：US18244069

申请日：2023-09-08

Applicant: Micron Technology, Inc.

Inventor： Eric S. Carman ,  Durai Vishak Nirmal Ramaswamy ,  Richard E Fackenthal ,  Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Duane R. Mills ,  Christian Caillat

IPC: H10B12/00 ,  H01L29/24 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4094

CPC classification number: H10B12/20 ,  H01L29/24 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4094 ,  H10B12/50 ,  H10B41/10

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

公开(公告)号：US11832454B2

公开(公告)日：2023-11-28

申请号：US17396049

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H10B99/00 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/24

CPC classification number: H10B99/00 ,  H01L27/092 ,  H01L27/124 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78642

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11783902B2

公开(公告)日：2023-10-10

申请号：US17709102

申请日：2022-03-30

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/3404 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of four possible data states by applying a first voltage pulse to the memory cell wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell wherein the second voltage pulse has a second polarity and a second magnitude, and the second voltage pulse is applied for a shorter duration than the first voltage pulse.

公开(公告)号：US20230298652A1

公开(公告)日：2023-09-21

申请号：US18200871

申请日：2023-05-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E. Fackenthal ,  Duane R. Mills

IPC: G11C11/404

CPC classification number: G11C11/404

Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

公开(公告)号：US20230268005A1

公开(公告)日：2023-08-24

申请号：US18309704

申请日：2023-04-28

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera

IPC: G11C16/10 ,  G11C11/56 ,  G06N3/08 ,  G06F11/10 ,  G06N3/04

CPC classification number: G11C16/10 ,  G06F11/1076 ,  G06N3/04 ,  G06N3/08 ,  G11C11/56 ,  G11C16/0483

Abstract: Systems, methods and apparatus to determine, in response to a command to write data into a set of memory cells, a programming mode of a set of memory cell to optimize performance in retrieving the data back from the set of memory cells. For example, based on usages of a memory region containing the memory cell set, a predictive model can be used to identify a combination of an amount of redundant information to be stored into the memory cells in the set and a programming mode of the memory cells to store the redundant information. Increasing the amount of redundant information can increase error recovery capability but increase bit error rate and/or increase time to read. The predictive model is trained to predict the combination to optimize read performance.

公开(公告)号：US20230195623A1

公开(公告)日：2023-06-22

申请号：US17556862

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Sandeep Krishna Thirumala ,  Lingming Yang ,  Karthik Sarpatwari ,  Nevil N. Gajera

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/72 ,  G06F2212/60

Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.

公开(公告)号：US20230031904A1

公开(公告)日：2023-02-02

申请号：US17388678

申请日：2021-07-29

Applicant: Micron Technology, Inc.

Inventor： Eric S. Carman ,  Durai Vishak Nirmal Ramaswamy ,  Richard E Fackenthal ,  Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Duane R. Mills ,  Christian Caillat

IPC: H01L27/108 ,  H01L29/24 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

公开(公告)号：US11568952B2

公开(公告)日：2023-01-31

申请号：US17337195

申请日：2021-06-02

Applicant: Micron Technology, Inc.

Inventor： Xuan-Anh Tran ,  Nevil N. Gajera ,  Karthik Sarpatwari ,  Amitava Majumdar

IPC: G11C29/44 ,  G11C29/46 ,  G11C29/12 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/00

Abstract: Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.