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    Post passivation metal scheme for high-performance integrated circuit devices
    31.
    发明授权
    Post passivation metal scheme for high-performance integrated circuit devices 有权
    后钝化金属方案用于高性能集成电路器件

    公开(公告)号：US06649509B1

    公开(公告)日：2003-11-18

    申请号：US09998862

    申请日：2001-10-24

    申请人： Mou-Shiung Lin ,  Ming-Ta Lei ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    发明人： Mou-Shiung Lin ,  Ming-Ta Lei ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    IPC分类号： H01L214763

    CPC分类号： H01L23/60 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/62 ,  H01L24/05 ,  H01L27/0248 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. The post passivation metal scheme is connected to external circuits through bond pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding, the composite metal is created over a bulk conduction metal. A diffusion metal may be applied between the bulk metal and the composite metal, in addition a layer of Under-Barrier-Metal (UBM) may be required underneath the bulk conduction metal.

    摘要翻译： 在已经被常规钝化层覆盖的IC器件的表面上提供了新的后钝化金属互连方案。 本发明的金属方案包括叠加常规的钝化层，厚和宽的金属线与厚的介电层和接合焊盘的组合。 本发明的互连系统可以用于将功率，接地，信号和时钟线从接合焊盘分配到设置在IC器件的任何位置的器件的电路，而不引入显着的功率下降。 后钝化金属方案通过接合焊盘，焊接，TAB接合等连接到外部电路。 互连金属方案的顶层使用用于引线键合的复合金属形成，复合金属在体导电金属上形成。 扩散金属可以施加在本体金属和复合金属之间，另外在体导电金属之下可能需要一层下阻挡金属（UBM）。

    Method for fabricating circuitry component
    33.
    发明授权
    Method for fabricating circuitry component 有权
    电路元件制造方法

    公开(公告)号：US08211791B2

    公开(公告)日：2012-07-03

    申请号：US10382699

    申请日：2003-03-05

    申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L21/76807 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

    摘要翻译： 芯片结构包括基板，第一堆叠层，钝化层和第二堆积层。 基板包括放置在基板的表面上的许多电气装置。 第一组合层位于基底上。 第一组合层设置有第一电介质体和第一互连方案，其中第一互连方案与第一介电体内部交错并电连接到电气装置。 第一互连方案由第一金属层和插塞构成，其中相邻的第一金属层通过插塞电连接。 钝化层设置在第一堆叠层上并且设有暴露第一互连方案的开口。 第二堆叠层形成在钝化层上。 第二组合层设置有第二电介质体和第二互连方案，其中第二互连方案在第二介电体内部交织并与第一互连方案电连接。 第二互连方案由至少一个第二金属层和至少一个通孔金属填料构成，其中第二金属层电连接到通孔金属填料。 第二金属层的迹线的厚度，宽度和横截面积分别大于第一金属层的厚度，宽度和横截面面积。