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    CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME
    1.
    发明申请
    CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME 有权
    芯片结构及其形成方法

    公开(公告)号：US20120098128A1

    公开(公告)日：2012-04-26

    申请号：US13277142

    申请日：2011-10-19

    申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L21/76807 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

    摘要翻译： 具有金属化结构的芯片和具有在金属化结构的第一和第二接触点上的第一和第二开口的绝缘层，连接第一和第二接触点的第一电路层，包括第一迹线部分，第一和第二通孔部分， 所述第一迹线部分和所述第一和第二接触点，所述第一电路层包括铜层和在所述铜层下面和所述第一迹线部分的侧壁处的第一导电层，以及第二电路层， 其第二通路部分在其底部，其中所述第二电路层包括另一铜层和位于所述另一铜层下方的第二导电层和所述第二迹线部分的侧壁处的第二导电层，以及第二电介质层， 第二电路层。

    Chip structure and process for forming the same
    8.
    发明授权
    Chip structure and process for forming the same 有权

    公开(公告)号：US06798073B2

    公开(公告)日：2004-09-28

    申请号：US10337668

    申请日：2003-01-06

    申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    IPC分类号： H01L2348

    CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L21/76807 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

    Post passivation metal scheme for high-performance integrated circuit devices
    9.
    发明授权
    Post passivation metal scheme for high-performance integrated circuit devices 有权
    后钝化金属方案用于高性能集成电路器件

    公开(公告)号：US06605528B1

    公开(公告)日：2003-08-12

    申请号：US10004027

    申请日：2001-10-24

    申请人： Mou-Shiung Lin ,  Ming-Ta Lei ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    发明人： Mou-Shiung Lin ,  Ming-Ta Lei ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    IPC分类号： H01L214763

    CPC分类号： H01L23/60 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/62 ,  H01L24/05 ,  H01L27/0248 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. No, or smaller ESD circuits are required due to the low impedance post-passivation interconnection, since any accumulated electrostatic discharge will be evenly distributed across all junction capacitance of the circuits on the chip. The post passivation metal scheme is connected to external circuits through bond pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding, the composite metal is created over a bulk conduction metal. A diffusion metal may be applied between the bulk metal and the composite metal, in addition a layer of Under-Barrier-Metal (UBM) may be required underneath the bulk conduction metal.

    摘要翻译： 在已经被常规钝化层覆盖的IC器件的表面上提供了新的后钝化金属互连方案。 本发明的金属方案包括叠加常规的钝化层，厚和宽的金属线与厚的介电层和接合焊盘的组合。 本发明的互连系统可以用于将功率，接地，信号和时钟线从接合焊盘分配到设置在IC器件的任何位置的器件的电路，而不引入显着的功率下降。 由于低阻抗钝化后互连，不需要或更小的ESD电路，因为任何累积的静电放电将均匀分布在芯片上电路的所有结电容上。 后钝化金属方案通过接合焊盘，焊接，TAB接合等连接到外部电路。 互连金属方案的顶层使用用于引线键合的复合金属形成，复合金属在体导电金属上形成。 扩散金属可以施加在本体金属和复合金属之间，另外在体导电金属之下可能需要一层下阻挡金属（UBM）。