公开(公告)号：US20150124418A1

公开(公告)日：2015-05-07

申请号：US14073756

申请日：2013-11-06

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Jonghae Kim

IPC: H05K1/16

CPC classification number: H05K1/165 ,  H05K1/141 ,  H05K2201/10378

Abstract: An embedded layered inductor is provided that includes a first inductor layer and a second inductor layer coupled to the first inductor layer. The first inductor layer comprises a patterned metal layer that may also be patterned to form pads. The second inductor layer comprises metal deposited in a dielectric layer adjacent the patterned metal layer.

Abstract translation: 提供了一种嵌入式分层电感器，其包括耦合到第一电感器层的第一电感器层和第二电感器层。 第一电感器层包括图案化的金属层，其也可以被图案化以形成焊盘。 第二电感器层包括沉积在邻近图案化金属层的电介质层中的金属。

公开(公告)号：US20140374914A1

公开(公告)日：2014-12-25

申请号：US13946135

申请日：2013-07-19

Applicant: QUALCOMM Incorporated

Inventor： Daeik D. Kim ,  Je-Hsiung Lan ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Changhan Yun

IPC: H01L23/00 ,  G06F17/50 ,  H01L21/02

CPC classification number: H01L23/562 ,  G06F17/5081 ,  G06F2217/80 ,  H01L21/02005 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

Abstract: An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device.

Abstract translation: 一种装置包括包括至少一层的装置。 所述至少一个层包括设备间应力补偿模式，其被配置为在所述设备从另一设备分离之前减少设备间翘曲的量。

公开(公告)号：US08889522B2

公开(公告)日：2014-11-18

申请号：US14076395

申请日：2013-11-11

Applicant: QUALCOMM Incorporated

Inventor： Woo Tag Kang ,  Jonghae Kim

IPC: H01L27/04 ,  H01L49/02 ,  H01L27/08 ,  H01L27/10

CPC classification number: H01L28/40 ,  H01L27/0805 ,  H01L27/101

Abstract: Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material.

Abstract translation: 提出了与多个高击穿电压嵌入式电容器相关的方法和装置。 半导体器件可以包括嵌入绝缘体中的栅极材料，多个金属触点和多个电容器。 多个电容器可以包括下电极，形成为覆盖下电极的表面的电介质和形成在电介质上的上电极。 此外，多个触点可以将多个电容器中的每个下电极连接到栅极材料。 多个电容器可以经由栅极材料串联连接。

公开(公告)号：US20140268615A1

公开(公告)日：2014-09-18

申请号：US13830033

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Changhan Yun ,  Francesco Carobolante ,  Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Lawrence D. Smith ,  Matthew M. Nowak

IPC: H05K7/10 ,  H05K3/30 ,  H05K3/10

CPC classification number: H05K1/165 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0262 ,  H05K3/0091 ,  H05K3/10 ,  H05K3/30 ,  H05K7/1092 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49147 ,  Y10T29/49156

Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

Abstract translation: 两级供电网络包括电压调节器和插入器。 插入器包括具有嵌入式电感器的封装衬底。 嵌入式电感器包括一组迹线和一组在迹线的相对端处的通过衬底通孔。 插入器耦合到电压调节器。 两级供电网络还包括由封装基板支撑的半导体管芯。 两级供电网络还包括由包装基板支撑的电容器。 电容器可操作以提供与半导体管芯相关联的去耦电容和电容，以降低电压调节器的开关噪声。

公开(公告)号：US08717118B2

公开(公告)日：2014-05-06

申请号：US13705655

申请日：2012-12-05

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Feng Wang ,  Matthew M. Nowak

IPC: H03H7/38

CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01L21/50 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor.

Abstract translation: 提出了倒装芯片电路组件的变压器信号耦合和阻抗匹配方法。 在一个实施例中，用于提供管芯之间的感应耦合的方法可以包括使用无源工艺在第一管芯上制造第一电感器，使用半导体工艺在第二管芯上制造第二电感器，以及将每个管芯组装成第一和第二 电感器被配置为变压器。 在另一个实施例中，用于使用倒装芯片技术制造的RF电路中的阻抗匹配的方法可以包括将RF输入信号传递通过使用无源过程形成的第一电感器，从而引起接近第二电感器的时变磁通量，所述第二电感器使用 激活过程，并且将由时变磁通感应的RF信号传递通过第二电感器。

公开(公告)号：US20130095576A1

公开(公告)日：2013-04-18

申请号：US13705655

申请日：2012-12-05

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Feng Wang ,  Matthew M. Nowak

IPC: H01L21/50

CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01L21/50 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor.

Abstract translation: 提出了倒装芯片电路组件的变压器信号耦合和阻抗匹配方法。 在一个实施例中，用于在管芯之间提供电感耦合的方法可以包括使用无源工艺在第一管芯上制造第一电感器，使用半导体工艺在第二管芯上制造第二电感器，以及将每个管芯组装成第一和第二 电感器被配置为变压器。 在另一个实施例中，用于使用倒装芯片技术制造的RF电路中的阻抗匹配的方法可以包括将RF输入信号传递通过使用无源过程形成的第一电感器，从而引起接近第二电感器的时变磁通量，所述第二电感器使用 激活过程，并且将由时变磁通感应的RF信号传递通过第二电感器。

公开(公告)号：US20250118645A1

公开(公告)日：2025-04-10

申请号：US18987457

申请日：2024-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L21/48 ,  H10D1/68

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

公开(公告)号：US12273095B2

公开(公告)日：2025-04-08

申请号：US17245901

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Kai Liu ,  Rui Tang ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H03H3/02 ,  H01P1/203 ,  H03H9/05 ,  H03H9/54

Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.

公开(公告)号：US12255381B2

公开(公告)日：2025-03-18

申请号：US17652328

申请日：2022-02-24

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01Q1/22 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L25/00 ,  H01L25/10

Abstract: Antenna modules employing three-dimensional (3D) build-up on mold package to support efficient integration of radio-frequency (RF) circuitry, and related fabrication methods. The antenna module includes a RF transceiver whose circuitry is split over multiple semiconductor dies (“dies”) so different semiconductor devices can be formed in different semiconductor structures. The antenna module is provided as a 3D build-up on mold package to reduce lengths of die-to-die (D2D) interconnections between circuits in different dies. First and second die packages that include respective first and second dies encapsulated in respective first and second mold layers are coupled to each other in a vertical direction in a 3D stacked arrangement with active faces of the first and second dies facing each other to provide a reduced distance between the active faces of the first and second dies. An antenna is stacked on the second die package to provide an antenna(s) for the antenna module.

公开(公告)号：US12155373B2

公开(公告)日：2024-11-26

申请号：US17450847

申请日：2021-10-14

Applicant: QUALCOMM Incorporated

Inventor： Kai Liu ,  Je-Hsiung Lan ,  Jonghae Kim

IPC: H03H9/54 ,  H03H3/02 ,  H03H9/05 ,  H10N30/071

Abstract: Disclosed is a radio frequency (RF) filter that vertically integrates an acoustic die with inductors formed in one or more layers above the acoustic die. The acoustic die may be over-molded so that the acoustic dome, important for maintaining acoustic integrity, may be protected.