公开(公告)号：US20160126345A1

公开(公告)日：2016-05-05

申请号：US14993671

申请日：2016-01-12

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro TAMAKI ,  Yoshito Nakazawa ,  Satoshi Eguchi

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396

Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

Abstract translation: 解决超结结构的以下问题的半导体装置：由于体细胞区域（有源区域）的相对高的浓度，在周边区域（周边区域或结合区域）中难以实现击穿电压 等于或高于通过常规的连接边缘端子结构或再结构的单元区域。 半导体器件包括通过沟槽填充技术在单元区域中形成的具有超结结构的功率MOSFET。 此外，在细胞区域周围的漂移区域中设置具有与细胞区域的侧面平行的取向的超结结构。

公开(公告)号：US09275863B2

公开(公告)日：2016-03-01

申请号：US14492382

申请日：2014-09-22

Applicant: RENESAS ELECTRONICS CORPORATION ,  HITACHI ULSI SYSTEMS CO., LTD.

Inventor： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract translation: 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的方向的深度方向上的第一导电类型的半导体层的主表面形成沟槽， 在沟槽的内表面上形成包括热氧化膜和沉积膜的栅极绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成 用作沟道形成区域的第二导电类型的半导体区域，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US09166017B2

公开(公告)日：2015-10-20

申请号：US14261497

申请日：2014-04-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Daisuke Arai ,  Yoshito Nakazawa ,  Ikuo Hara ,  Tsuyoshi Kachi ,  Yoshinori Hoshino ,  Tsuyoshi Tabata

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/739 ,  H01L29/06

CPC classification number: H01L29/66325 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/7395

Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

Abstract translation: 提供了能够提高能够降低稳定损耗，关断时间和关断损耗的IGBT的产量的技术。 在形成在基板的主表面上的层间绝缘膜中形成开口时，在氮化硅膜上一次停止对PSG膜的叠层绝缘膜，SOG膜和氧化硅膜的蚀刻。 然后，依次蚀刻氮化硅膜和氧化硅膜以形成开口。 结果，防止了开口穿过厚度为20至100nm的n型源极层和p +型发射极层并到达衬底。

公开(公告)号：US08981469B2

公开(公告)日：2015-03-17

申请号：US14037103

申请日：2013-09-25

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro Tamaki ,  Yoshito Nakazawa

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40

CPC classification number: H01L29/0634 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7825

Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

Abstract translation: 解决了与各种工艺参数相对较轻的波动引起的n沟道功率MOSFET等相关的问题：源极 - 漏极击穿电压通过靠近p型体区域的端部的击穿而减小 到由该区域的电场浓度引起的活性单元区域与芯片周边部分之间的环状中间区域附近的部分。 为了解决这个问题，在第一导电类型的有源电池区域，芯片外围区域和位于它们之间的中间区域的各个漂移区域中，具有超结构结构的功率半导体器件采取以下措施： 使包括中间区域中的超结构结构的第二导电类型的列区域中的至少一个比其它区域的宽度大。

公开(公告)号：US08937350B2

公开(公告)日：2015-01-20

申请号：US14170430

申请日：2014-01-31

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi Matsuura ,  Yoshito Nakazawa ,  Tsuyoshi Kachi ,  Yuji Yatsuda

IPC: H01L27/108 ,  H01L29/78 ,  H01L27/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/872 ,  H01L21/265 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

公开(公告)号：US08796787B2

公开(公告)日：2014-08-05

申请号：US14040483

申请日：2013-09-27

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro Tamaki ,  Yoshito Nakazawa

IPC: H01L27/088

CPC classification number: H01L29/7811 ,  H01L23/3107 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7816 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/29099

Abstract: In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Abstract translation: 在诸如在有源单元区域和芯片外围区域中的每一个中具有超结结构的功率MOSFET的半导体功率器件中，第二导电类型的表面区域的外端与第二导电性的主结 类型在第一导电类型的漂移区的表面中并且具有低于主结的浓度的漂移区的表面位于主结的外端和超结结构的外端之间的中间区域 芯片外围区域。

公开(公告)号：US08558309B2

公开(公告)日：2013-10-15

申请号：US13731065

申请日：2012-12-30

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro Tamaki ,  Yoshito Nakazawa

IPC: H01L29/76

CPC classification number: H01L29/0634 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7825

Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.