公开(公告)号：US07223691B2

公开(公告)日：2007-05-29

申请号：US10965031

申请日：2004-10-14

申请人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Patrick W. DeHaven ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Terry A. Spooner ,  Tsong-Lin L. Tai ,  Kwong Hon Wong ,  Chin-Chao Yang

发明人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Patrick W. DeHaven ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Terry A. Spooner ,  Tsong-Lin L. Tai ,  Kwong Hon Wong ,  Chin-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76888

摘要： A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.

摘要翻译： 具有低接触电阻和改进的可靠性的新颖的层间接触通孔结构以及形成接触通孔的方法。 该方法包括以下步骤：通过层间电介质层蚀刻开口以暴露下面的金属（铜）层表面; 并且将惰性气体（氮气）的低能量离子注入进入下面暴露的金属; 并且将耐火衬垫沉积到壁和底部通孔结构中，由于进行的惰性气体注入的存在而将具有较低的接触电阻。 优选地，惰性氮气与下面暴露的铜金属反应形成一层薄的CuN。

公开(公告)号：US07208414B2

公开(公告)日：2007-04-24

申请号：US10711365

申请日：2004-09-14

申请人： Anthony G. Domenicucci ,  Bradley P. Jones ,  Christian Lavoie ,  Robert J. Purtell ,  Yun Yu Wang ,  Kwong Hon Wong

发明人： Anthony G. Domenicucci ,  Bradley P. Jones ,  Christian Lavoie ,  Robert J. Purtell ,  Yun Yu Wang ,  Kwong Hon Wong

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665

摘要： The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure. A second anneal is performed to convert the metal rich silicide phase formed by the two thermal cycles of the first anneal into a metal silicide phase that is in its lowest resistance phase. A metal silicide is provided whose thickness is self-limiting.

摘要翻译： 本发明提供了一种通过使用含金属的硅合金与进行两个不同的热循环的第一次退火相结合的方法来增强金属在硅化过程中的单向扩散。 第一退火的第一热循环在能够增强金属例如Co和/或Ni的单向扩散到含Si层中的温度下进行。 第一热循环导致形成含非晶态金属的硅化物。 第二热循环在将含非晶态金属的硅化物转化为与含金属的硅合金层或纯金属含有层相比基本上不可蚀刻的结晶的富含金属的硅化物的温度下进行。 在第一退火之后，执行选择性蚀刻以从结构中除去任何未反应的含金属合金层。 执行第二退火以将由第一退火的两个热循环形成的富金属硅化物相转换成处于其最低电阻相的金属硅化物相。 提供了一种金属硅化物，其厚度是自限制的。

公开(公告)号：US07088074B2

公开(公告)日：2006-08-08

申请号：US10039541

申请日：2002-01-02

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H02J7/00

CPC分类号： H01M10/425 ,  H01L23/58 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01M2/1066 ,  H01M2/204 ,  H01L2924/00014 ,  H01L2924/00

摘要： A system level device for battery and integrated circuit chip integration comprises at least one battery; at least one integrated circuit chip powered by the at least one battery; and a package connected to any of the at least one battery and the at least one integrated circuit chip, wherein the at least one battery connects to a pair of opposed upright ends of the package, wherein the at least one integrated circuit chip is disposed between the at least one battery and the package, and wherein the at least one integrated circuit chip lays on top of a portion of the package.

摘要翻译： 用于电池和集成电路芯片集成的系统级装置包括至少一个电池; 由所述至少一个电池供电的至少一个集成电路芯片; 以及连接到所述至少一个电池和所述至少一个集成电路芯片中的任一个的封装，其中所述至少一个电池连接到所述封装的一对相对的直立端，其中所述至少一个集成电路芯片设置在 所述至少一个电池和所述封装，并且其中所述至少一个集成电路芯片放置在所述封装的一部分的顶部上。

公开(公告)号：US07037824B2

公开(公告)日：2006-05-02

申请号：US10844533

申请日：2004-05-13

申请人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

发明人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

公开(公告)号：US06909145B2

公开(公告)日：2005-06-21

申请号：US10252661

申请日：2002-09-23

申请人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Joseph F. Shepard, Jr. ,  Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Joseph F. Shepard, Jr. ,  Kwong Hon Wong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6653 ,  H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6659

摘要： A method and structure for a metal oxide semiconductor transistor having a substrate, a well region in the substrate, source and drain regions on opposite sides of the well region in the substrate, a gate insulator over the well region of the substrate, a polysilicon gate conductor over the gate insulator, and metallic spacers on sides of the gate conductor.

摘要翻译： 一种金属氧化物半导体晶体管的方法和结构，其具有衬底，衬底中的阱区，衬底中的阱区的相对侧上的源极和漏极区，衬底的阱区上的栅极绝缘体，多晶硅栅极 栅极绝缘体上的导体，以及栅极导体侧面的金属间隔物。

公开(公告)号：US06768063B2

公开(公告)日：2004-07-27

申请号：US09943827

申请日：2001-08-31

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H05K111

CPC分类号： H05K3/24 ,  G01N27/226 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for an electrode device, whereby a second electrode is deposited on a first electrode such that there is an increase in the capacitive coupling between the pair of conductive electrodes. The electrodes are self-aligning such that the patterning manufacturing process is insensitive to variations in the positional placement of the pattern on the substrate. Moreover, a single lithographic masking layer is used for forming the pair of electrodes, which are electrically isolated. Finally, the first electrode is offset from the second electrode by a chemical surface modification of the first electrode, and an anisotropic deposition of the second electrode which is shadowed by the first electrode.

摘要翻译： 一种电极装置的方法和结构，由此第二电极沉积在第一电极上，使得一对导电电极之间的电容耦合增加。 电极是自对准的，使得图案化制造工艺对图案在衬底上的位置放置的变化不敏感。 此外，单个光刻掩模层用于形成电隔离的一对电极。 最后，第一电极通过第一电极的化学表面改性和由第一电极遮蔽的第二电极的各向异性沉积而偏离第二电极。

公开(公告)号：US06620657B2

公开(公告)日：2003-09-16

申请号：US10052151

申请日：2002-01-15

申请人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H01L2100

CPC分类号： H01L51/0001 ,  H01L51/0024 ,  H01L51/0516 ,  H01L51/0541 ,  H01L51/0545

摘要： A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistors made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.

摘要翻译： 通过使用第一平面载体来形成包括栅极，源极，漏极和主体元件的器件的第一部分来形成完全平坦化的聚合物薄膜晶体管的结构和方法。 优选地，由所有有机材料制成的薄膜晶体管。 栅极电介质可以是高k聚合物，以提高器件性能。 然后，部分完成的装置结构被颠倒翻转并转移到第二平面载体。 然后施加一层蜡或光敏有机材料，并且可以用作临时胶。 然后通过蚀刻工艺限定该装置，包括其身体区域。 与器件的接触通过导电材料沉积和化学机械抛光形成。

公开(公告)号：US06528383B1

公开(公告)日：2003-03-04

申请号：US10016016

申请日：2001-12-12

申请人： Satya N. Chakravarti ,  Ashima B. Chakravarti ,  Irene L. McStay ,  Kwong Hon Wong

发明人： Satya N. Chakravarti ,  Ashima B. Chakravarti ,  Irene L. McStay ,  Kwong Hon Wong

IPC分类号： H01L2100

CPC分类号： H01L27/10894 ,  H01L27/0676 ,  H01L27/0802 ,  H01L27/10861 ,  H01L28/20 ,  H01L28/40

摘要： A compact resistor is formed in an integrated circuit using many of the same steps as are employed in forming a trench capacitor for a DRAM cell; in particular depositing a layer of heavily doped germanium in the trench interior after the step of doping the substrate to form the bottom plate for the capacitor, depositing polysilicon having the required resistivity in the trench then removing the germanium and leaving only enough to form an ohmic contact in the trench bottom.

摘要翻译： 使用与形成用于DRAM单元的沟槽电容器相同的步骤中的许多步骤，在集成电路中形成紧凑型电阻器; 特别是在掺杂衬底以形成用于电容器的底板的步骤之后在沟槽内部沉积重掺杂的锗层，在沟槽中沉积具有所需电阻率的多晶硅，然后除去锗并仅留下足以形成欧姆 接触沟槽底部。

公开(公告)号：US06509265B1

公开(公告)日：2003-01-21

申请号：US09666240

申请日：2000-09-21

申请人： Patrick W. DeHaven ,  Anthony G. Domenicucci ,  Lynne M. Gignac ,  Glen L. Miles ,  Prabhat Tiwari ,  Yun-Yu Wang ,  Horatio S. Wildman ,  Kwong Hon Wong

发明人： Patrick W. DeHaven ,  Anthony G. Domenicucci ,  Lynne M. Gignac ,  Glen L. Miles ,  Prabhat Tiwari ,  Yun-Yu Wang ,  Horatio S. Wildman ,  Kwong Hon Wong

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/28518 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76864

摘要： A process for forming a conductive contact having a flat interface. A layer containing niobium and titanium is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500° C. to about 700° C. By this process, a flatter interface between silicide and silicon, which is less likely to cause junction leakage, is formed on annealing. The step of annealing also produces a more uniform bilayer, which is a better barrier against tungsten encroachment during subsequent tungsten deposition. Larger silicide grains are also formed so that fewer grain boundaries are produced, reducing metal diffusion in grain boundaries. The process can be used to form contacts for very small devices and shallow junctions, such as are required for current and future semiconductor devices.

摘要翻译： 一种用于形成具有平坦界面的导电触头的工艺。 将含有铌和钛的层沉积在硅衬底上，所得结构在约500℃至约700℃的含氮气氛中退火。通过该过程，硅化物和硅之间的平坦界面是 在退火时形成不太可能导致结漏电。 退火步骤还产生更均匀的双层，这是在随后的钨沉积期间防止钨侵蚀的更好的屏障。 还形成更大的硅化物晶粒，使得产生更少的晶界，减少晶界中的金属扩散。 该过程可用于形成非常小的器件和浅结的接触，例如当前和未来的半导体器件所需要的。

公开(公告)号：US07683418B2

公开(公告)日：2010-03-23

申请号：US12277539

申请日：2008-11-25

申请人： Dae-Gyu Park ,  Oleg G. Gluschenkov ,  Michael A. Gribelyuk ,  Kwong Hon Wong

发明人： Dae-Gyu Park ,  Oleg G. Gluschenkov ,  Michael A. Gribelyuk ,  Kwong Hon Wong

IPC分类号： H01L27/108

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.

摘要翻译： 本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。