公开(公告)号：US20090200636A1

公开(公告)日：2009-08-13

申请号：US12029800

申请日：2008-02-12

申请人： Daniel C. Edelstein ,  Nicholas C. M. Fuller ,  David V. Horak ,  Elbert E. Huang ,  Wai-Kin Li ,  Anthony D. Lisi ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Daniel C. Edelstein ,  Nicholas C. M. Fuller ,  David V. Horak ,  Elbert E. Huang ,  Wai-Kin Li ,  Anthony D. Lisi ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/00 ,  H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

摘要： Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.

摘要翻译： 公开了亚光刻尺寸气隙形成和相关结构。 在一个实施例中，一种方法包括在衬底上形成包括互连的介质层; 在电介质层上沉积盖层; 在所述盖层上沉积光致抗蚀剂; 图案化光致抗蚀剂以包括最多部分地覆盖互连的第一沟槽图案; 在所述第一沟槽图案内形成间隔物以形成具有亚光刻尺寸的第二沟槽图案; 将所述第二沟槽图案转移到所述覆盖层中并进入所述互连之间的所述介电层; 并且通过夹住介电层中的沟槽而沉积另一介质层以形成气隙。

公开(公告)号：US20090148677A1

公开(公告)日：2009-06-11

申请号：US11953359

申请日：2007-12-10

申请人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

发明人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

IPC分类号： C25D5/02 ,  B32B3/00

CPC分类号： C25D5/02 ,  Y10T428/24331 ,  Y10T428/24917

摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.

摘要翻译： 公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料 没有接缝和/或空隙。 此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层 金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

公开(公告)号：US20090140428A1

公开(公告)日：2009-06-04

申请号：US11949189

申请日：2007-12-03

申请人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

摘要翻译： 在包括低k材料层和嵌入其中的金属特征的互连结构上形成硬掩模。 将嵌段聚合物施加到硬掩模层上，自组装和图案化以形成聚合物嵌段组分的聚合物基质并且包含圆柱形孔。 蚀刻硬掩模和低k材料层以形成空腔。 导电材料镀在暴露的金属表面上，包括金属特征的顶表面的部分以形成金属垫。 金属硅化物焊盘通过将金属焊盘暴露于含硅气体而形成。 进行蚀刻以放大和合并低k材料层中的空腔。 通过金属硅化物焊盘防止金属特征被蚀刻。 形成具有空隙并且没有金属特征表面的缺陷的互连结构。

公开(公告)号：US20090075472A1

公开(公告)日：2009-03-19

申请号：US11857760

申请日：2007-09-19

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US20090032959A1

公开(公告)日：2009-02-05

申请号：US11831236

申请日：2007-07-31

申请人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

发明人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

IPC分类号： H01L23/52

CPC分类号： H01L23/5256 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.

摘要翻译： 提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。 包括导体或半导体的导电结构形成在半导体衬底上。 在导电结构上形成至少一个绝缘体层。 在所述至少一个绝缘体层中形成凹陷区域。 将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。 第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。 具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。 形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

公开(公告)号：US20080296728A1

公开(公告)日：2008-12-04

申请号：US11755995

申请日：2007-05-31

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Jack A. Mandelman ,  Louis L. Hsu

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Jack A. Mandelman ,  Louis L. Hsu

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.

摘要翻译： 提供了一种保险丝/反熔丝结构，其中抗熔丝的编程由邻近熔丝元件形成的电动诱发小丘引起。 小丘破裂位于熔丝元件的侧壁上的薄的扩散阻挡层，并且熔丝元件内的导电材料扩散到相邻的介电材料中。 保险丝元件包括位于线路开口内的导电材料，该导电材料包括具有第一厚度的第一扩散阻挡层，位于侧壁上的第一厚度和线路开口的底壁。 抗熔丝元件包括位于组合的通孔和线路开口内的导电材料，其包括位于组合的通路和线路开口的侧壁上的第一扩散阻挡层和具有大于第二扩散阻挡层的第二厚度的第二扩散阻挡层 第一厚度位于第一扩散阻挡层上。

公开(公告)号：US20080173976A1

公开(公告)日：2008-07-24

申请号：US11626548

申请日：2007-01-24

申请人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

发明人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/0688 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

摘要翻译： 提供了一种用于制造微电子芯片的方法，该微电子芯片包括覆盖气隙的诸如电感器的无源器件。 在这种方法中，在微电子芯片的半导体区域中形成多个前端（“FEOL”）器件，并且形成多个层叠的层间电介质（“ILD”）层以覆盖多个 的多个层叠的ILD层，包括第一ILD层和第二ILD层，其中第二ILD层抵抗攻击第一ILD层的第一蚀刻剂的侵袭。 形成无源器件至少覆盖第一ILD层。 使用第一蚀刻剂，除去与无源器件对准的第一ILD层的一部分，以形成与被动器件对准的无源器件下方的气隙。

公开(公告)号：US20080164613A1

公开(公告)日：2008-07-10

申请号：US11621709

申请日：2007-01-10

申请人： Daniel C. Edelstein ,  Stephen M. Rossnagel

发明人： Daniel C. Edelstein ,  Stephen M. Rossnagel

IPC分类号： H01L23/48 ,  H01L21/288

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper interconnection structure which is electroplated onto a silicon layer or semiconductor substrate. The structure includes an ultra-thin copper seed alloy incorporating selectively minor amounts of a dopant material to facilitate a continuous deposition thereof onto the silicon layer or semiconductor substrate. The copper seed alloy may contain dopant material selected from the group of materials consisting of Ru, Ir, Pt, Pd and alloys thereof. Furthermore, there is provided a method for producing the structure.

摘要翻译： 电镀在硅层或半导体衬底上的铜互连结构。 该结构包括超薄铜种子合金，其选择性地少量掺杂材料，以促进其连续沉积到硅层或半导体衬底上。 铜种子合金可以含有选自由Ru，Ir，Pt，Pd及其合金组成的材料组的掺杂剂材料。 此外，提供了一种制造该结构的方法。

公开(公告)号：US20080132027A1

公开(公告)日：2008-06-05

申请号：US11954782

申请日：2007-12-12

申请人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Kevin S. Petrarca ,  Anthony K. Stamper ,  Richard P. Volant

发明人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Kevin S. Petrarca ,  Anthony K. Stamper ,  Richard P. Volant

IPC分类号： H01L21/20

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.

摘要翻译： 公开了避免半导体器件小型化的问题的电阻器及相关方法。 在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。 在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。 这两个实施方案可以单独使用或一起使用。 还公开了用于产生电阻器的相关方法。

公开(公告)号：US20080122106A1

公开(公告)日：2008-05-29

申请号：US11518773

申请日：2006-09-11

申请人： Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Poncth

发明人： Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Poncth

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/7682

摘要： A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.

摘要翻译： 在具有转印到电介质层上的图案的电介质层和在图案周围的电介质层上转移的自对准阻挡掩模的衬底上产生气隙的结构和方法。