公开(公告)号：US09779832B1

公开(公告)日：2017-10-03

申请号：US15371462

申请日：2016-12-07

Applicant: SanDisk Technologies LLC

Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta ,  Jong Yuh

IPC: G11C7/10 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/16 ,  G11C16/08 ,  G11C7/22

CPC classification number: G11C16/3459 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3495

Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.

公开(公告)号：US09761290B1

公开(公告)日：2017-09-12

申请号：US15247912

申请日：2016-08-25

Applicant: SanDisk Technologies LLC

Inventor： Navneeth Kankani ,  Ning Ye ,  Suresh Upadhyayula ,  Sarath Puthenthermadam ,  Deepanshu Dutta

IPC: G11C5/02 ,  G11C7/20 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L23/467 ,  G11C7/24

CPC classification number: G11C7/20 ,  G11C5/02 ,  G11C5/04 ,  G11C7/04 ,  G11C7/24 ,  G11C16/20 ,  G11C29/52 ,  G11C2029/0409 ,  H01L23/345 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/467 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83805 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for preventing overheating, for annealing non-volatile memory. An apparatus may include an array of non-volatile storage elements. A heating element may be configured to heat a first set of the non-volatile storage elements to anneal the first set of non-volatile storage elements. A heat shield or cooling element may be configured to prevent a second set of the non-volatile storage elements from overheating during annealing of the first set of non-volatile storage elements, to mitigate data errors for data stored on the second set of non-volatile storage elements.

公开(公告)号：US20170178736A1

公开(公告)日：2017-06-22

申请号：US15385454

申请日：2016-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Xiaochang Miao ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2211/5648

Abstract: Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.

公开(公告)号：US09653154B2

公开(公告)日：2017-05-16

申请号：US14860086

申请日：2015-09-21

Applicant: SanDisk Technologies LLC

Inventor： Cynthia Hua-Ling Hsu ,  Aaron Lee ,  Abhijeet Manohar ,  Deepanshu Dutta

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/3459

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

公开(公告)号：US09552171B2

公开(公告)日：2017-01-24

申请号：US14526870

申请日：2014-10-29

Applicant: SanDisk Technologies LLC

Inventor： Yichao Huang ,  Chris Avila ,  Dana Lee ,  Henry Chin ,  Deepanshu Dutta ,  Sarath Puthenthermadam ,  Deepak Raghu

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G11C16/04 ,  G11C16/34

CPC classification number: G06F3/0647 ,  G06F3/0608 ,  G06F3/0679 ,  G06F12/0223 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/3431 ,  G11C16/349 ,  G11C16/3495 ,  G11C2211/5644 ,  G11C2211/5648

Abstract: A number of complimentary techniques for the read scrub process using adaptive counter management are presented. In one set of techniques, in addition to maintaining a cumulative read counter for a block, a boundary word line counter can also be maintained to track the number of reads to most recently written word line or word lines of a partially written block. Another set of techniques used read count threshold values that vary with the number of program/erase cycles that a block has undergone. Further techniques involve setting the read count threshold for a closed (fully written) block based upon the number reads it experienced prior to being closed. These techniques can also be applied at a sub-block, zone level.

Abstract translation: 提出了一些使用自适应计数器管理的读取擦除过程的免费技术。 在一组技术中，除了维持块的累积读计数器之外，还可以维持边界字行计数器以跟踪部分写入块的最近写入的字线或字线的读数。 使用的另一组技术读取计数阈值随着块所经历的编程/擦除周期数而变化。 进一步的技术涉及基于在关闭之前经历的数字读取来设置关闭（完全写入）块的读取计数阈值。 这些技术也可以应用于子区块级别。

公开(公告)号：US12254931B2

公开(公告)日：2025-03-18

申请号：US17845060

申请日：2022-06-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Jiacen Guo ,  Takayuki Inoue ,  Hua-Ling Hsu

IPC: G11C16/34 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

Abstract: An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.

公开(公告)号：US12249378B2

公开(公告)日：2025-03-11

申请号：US17666810

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.

公开(公告)号：US20240212764A1

公开(公告)日：2024-06-27

申请号：US18355348

申请日：2023-07-19

Applicant: SanDisk Technologies LLC

Inventor： Parth Amin ,  Anubhav Khandelwal ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/14

CPC classification number: G11C16/3445 ,  G11C16/14

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells disposed in a plurality of planes. The control circuit is configured to concurrently erase a block of memory cells in each of the plurality of planes, determine that the concurrent erase failed, disconnect a first one of the planes from the plurality of planes to form first remaining planes, and concurrently erase a block of memory cells in each of the first remaining planes.

公开(公告)号：US20240079068A1

公开(公告)日：2024-03-07

申请号：US17939748

申请日：2022-09-07

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta ,  Peng Zhang ,  Heguang Li

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3427 ,  G11C16/10 ,  G11C16/26

Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks and the plurality of sub-blocks includes a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines; and control circuitry coupled to the block of N wordlines. The control circuitry is configured to: perform a program operation in a normal order programming sequence on the first sub-block; perform a sensing operation on the first sub-block using a reverse sensing scheme; perform a program operation in a reverse order programming sequence on the second sub-block; and perform a sensing operation on the second sub-block using a regular sensing scheme.

公开(公告)号：US11798625B2

公开(公告)日：2023-10-24

申请号：US17469016

申请日：2021-09-08

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C11/5671 ,  H10B43/10 ,  H10B43/27

Abstract: An apparatus includes a control circuit configured to connect to first word lines of a first vertical sub-block and second word lines of a second vertical sub-block. The first vertical sub-block and the second vertical sub-block include memory cells connected in series in NAND strings, each NAND string including memory cells coupled to the first word lines in series with memory cells connected to the second word lines. The control circuit is configured to program or sense memory cells along a selected first word line of the first vertical sub-block while applying a first voltage to second word lines that are connected to programmed memory cells and applying a second voltage to second word lines that are connected to unprogrammed memory cells.