公开(公告)号：US10097167B2

公开(公告)日：2018-10-09

申请号：US15652316

申请日：2017-07-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: H03K3/356 ,  H03K3/037 ,  H03K19/00 ,  H03K19/20

Abstract: To provide an asynchronous circuit capable of power gating, a semiconductor device is configured with first to third terminals, a latch circuit, and a memory circuit. The third terminal outputs “false” when “false” is input to the first terminal and the second terminal. The third terminal outputs “true” when “true” is input to the first terminal and the second terminal. The third terminal outputs a truth value that is the same as the previous output, when “true” is input to one of the first terminal and the second terminal and “false” is input to the other of the first terminal and the second terminal. The memory circuit is capable of storing data stored in the latch circuit, while supply of a power supply voltage is stopped. The memory circuit includes a transistor that contains a metal oxide in a channel formation region.

公开(公告)号：US10074687B2

公开(公告)日：2018-09-11

申请号：US15708527

申请日：2017-09-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: H01L29/08 ,  H01L27/146 ,  H01L31/032 ,  H01L29/24 ,  H01L31/0272

CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14667 ,  H01L29/24 ,  H01L31/0272 ,  H01L31/0322

Abstract: A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.

公开(公告)号：US10033379B2

公开(公告)日：2018-07-24

申请号：US15412094

申请日：2017-01-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kurokawa ,  Yuki Okamoto

IPC: G11C5/14 ,  H03K17/687 ,  H03K3/03 ,  H03L7/099 ,  H01L27/12 ,  H03B5/00 ,  G11C7/12

Abstract: To generate an analog current without restriction by a power supply voltage. A semiconductor device includes a first node, a second node, a first- to an n-th-stage power storage element (n is an integer greater than or equal to 2), and a first- to an n-th-stage switch. The capacities of the first- to the n-th-stage power storage element are different from one another. The first- to the n-th-stage power storage element are electrically connected in parallel between the first node and the second node. A first terminal of a k-th stage power storage element (k is an integer greater than or equal to 1 and less than or equal to n) is electrically connected to the first input node via a k-th stage switch. The on/off states of the first- to the n-th-stage switch are controlled by a first to an n-th signal.

公开(公告)号：US10027324B2

公开(公告)日：2018-07-17

申请号：US15471516

申请日：2017-03-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Kozuma ,  Yoshiyuki Kurokawa

IPC: G06F7/38 ,  H03K19/00 ,  H03K19/177 ,  H03K21/02

Abstract: Skew of a multi-context PLD in context switch is reduced to achieve low power consumption. The frequency of a clock signal is switched in context switch operation in accordance with circuit operation to secure time required for context switch. By returning the frequency of the clock signal to the original frequency after executing the context switch, the PLD can maintain high-speed processing and perform the context switch accurately and safely. The time required for the context switch mainly depends on a hardware structure (circuit layout including a parasitic component). Thus, the reliability in the context switch can be improved when time that is equal to or longer than the longest time required for circuit change is secured.

公开(公告)号：US10002656B2

公开(公告)日：2018-06-19

申请号：US15138318

申请日：2016-04-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma

IPC: G11C7/16 ,  G11C11/24 ,  G11C16/04 ,  G11C16/10 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  H01L27/1156 ,  G11C27/00 ,  G11C27/02 ,  G11C11/40 ,  H01L21/02 ,  H01L23/528 ,  H01L27/105 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: G11C11/24 ,  G11C7/16 ,  G11C11/40 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0441 ,  G11C16/10 ,  G11C27/005 ,  G11C27/02 ,  G11C27/024 ,  H01L21/02565 ,  H01L21/0262 ,  H01L23/528 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit. The first circuit converts a digital signal input from the first memory circuit into an analog signal. The first memory circuit includes an input node, an output node, a transistor, and a capacitor. The capacitor is electrically connected to the output node. The transistor can control a conduction state between the input node and the output node. An analog signal is input to the input node from the first circuit. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

公开(公告)号：US09990207B2

公开(公告)日：2018-06-05

申请号：US14612356

申请日：2015-02-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/44

CPC classification number: G06F9/4401

Abstract: A semiconductor device with improved operating speed is provided. A semiconductor device including a memory circuit has a function of storing a start-up routine in the memory circuit and executing the start-up routine, a function of operating the memory circuit as a buffer memory device after executing the start-up routine, and a function of loading the start-up routine into the memory circuit from outside before the semiconductor device is powered off.

公开(公告)号：US09985069B2

公开(公告)日：2018-05-29

申请号：US14740720

申请日：2015-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Hikaru Tamura ,  Munehiro Kozuma

IPC: H01L29/10 ,  H01L27/146 ,  G02F1/1362 ,  H04N5/378 ,  H01L27/12 ,  G02F1/133

CPC classification number: H01L27/14643 ,  G02F1/1362 ,  G02F2001/13312 ,  H01L27/1225 ,  H01L27/14632 ,  H01L27/1464 ,  H04N5/378

Abstract: An object is to achieve low-power consumption by reducing the off-state current of a transistor in a photosensor. A semiconductor device including a photosensor having a photodiode, a first transistor, and a second transistor; and a read control circuit including a read control transistor, in which the photodiode has a function of supplying charge based on incident light to a gate of the first transistor; the first transistor has a function of storing charge supplied to its gate and converting the charge stored into an output signal; the second transistor has a function of controlling reading of the output signal; the read control transistor functions as a resistor converting the output signal into a voltage signal; and semiconductor layers of the first transistor, the second transistor, and the read control transistor are formed using an oxide semiconductor.

公开(公告)号：US09929736B2

公开(公告)日：2018-03-27

申请号：US15281151

申请日：2016-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki Okamoto ,  Yoshiyuki Kurokawa

IPC: H03L7/06 ,  H03L7/099 ,  H03K3/356 ,  H03K17/0412 ,  H03K17/687 ,  H01L29/786 ,  H03K3/03 ,  H03K5/131 ,  H01L27/12 ,  H03K5/26 ,  H03L7/093

CPC classification number: H03L7/0995 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78693 ,  H03K3/0315 ,  H03K3/356086 ,  H03K5/131 ,  H03K5/26 ,  H03K17/04123 ,  H03K17/687 ,  H03L7/093 ,  H03L7/099

Abstract: A novel PLL is provided. An oscillator circuit includes first to n-th inverters, and first and second circuits. A first terminal of each of the first and second circuits is electrically connected to an output terminal of the i-th inverter. A second terminal of each of the first and second circuits is electrically connected to an input terminal of the (i+1)-th inverter. The first circuit has functions of storing first data, switching between electrically disconnecting the first terminal and the second terminal from each other and setting a resistance between the first terminal and the second terminal to a value based on the first data. The second circuit has functions of storing second data, switching between electrically disconnecting the first terminal and the second terminal from each other and setting a resistance between the first terminal and the second terminal to a value based on the second data.

公开(公告)号：US09905598B2

公开(公告)日：2018-02-27

申请号：US14688406

申请日：2015-04-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masayuki Sakakura ,  Yoshiyuki Kurokawa

IPC: H01L29/82 ,  H01L27/146 ,  H01L29/786

CPC classification number: H01L27/14629 ,  H01L27/14612 ,  H01L27/14623 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L29/7869

Abstract: An image-capturing device which is capable of capturing high quality images and can be formed at a low cost is provided. The image-capturing device includes a first circuit including a first transistor and a second transistor, and a second circuit including a third transistor and a photodiode. The first transistor is provided on a first surface of a silicon substrate. The second transistor is provided over the first transistor. The photodiode is provided to the silicon substrate. The silicon substrate includes a second insulating layer surrounding a side surface of the photodiode. The first transistor is a p-channel transistor including an active region in the silicon substrate. The third transistor is an n-channel transistor including an oxide semiconductor layer as an active layer. A light-receiving surface of the photodiode is a surface of the silicon substrate opposite to the first surface.

公开(公告)号：US09869716B2

公开(公告)日：2018-01-16

申请号：US14612745

申请日：2015-02-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: G01R31/28 ,  G11C29/36 ,  H01L27/06 ,  G01R31/3181 ,  G11C11/16 ,  H01L27/10

CPC classification number: G01R31/2884 ,  G01R31/31813 ,  G11C11/16 ,  G11C29/36 ,  G11C2029/3602 ,  H01L27/0688 ,  H01L27/101

Abstract: Provided is a device capable of generating test patterns even after the design stage. The area of a circuit which is included in the device and unnecessary during normal operation can be reduced. The device includes a first circuit and a second circuit. The second circuit includes a plurality of third circuits, a plurality of fourth circuits, and a fifth circuit and has a function of generating a signal for testing operation of the first circuit and a function of operating as part of the first circuit. The fourth circuit has a function of storing a first data and a function of storing a second data. The fifth circuit has a function of writing the first data to the plurality of fourth circuits, a function of writing the second data to the plurality of fourth circuits, and a function of reading the second data from the plurality of fourth circuits.