公开(公告)号：US20180047610A1

公开(公告)日：2018-02-15

申请号：US15729842

申请日：2017-10-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Chang-Lun Lu

IPC: H01L21/683 ,  H01L21/66 ,  H01L23/373 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L25/16 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/568 ,  H01L22/14 ,  H01L23/147 ,  H01L23/373 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2224/45099

Abstract: An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.

公开(公告)号：US20180042112A1

公开(公告)日：2018-02-08

申请号：US15295010

申请日：2016-10-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Cheng-Hsiang Liu ,  Chang-Lun Lu ,  Jun-Cheng Liao ,  Cheng-Yi Chen

IPC: H05K1/18 ,  H05K3/34 ,  H05K1/11

CPC classification number: H05K1/181 ,  H05K1/111 ,  H05K3/341 ,  H05K3/3442 ,  H05K2201/09663 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic device includes a circuit board having a plurality of conductive contacts, and an electronic component disposed on the circuit board and having a plurality of electrode terminals. The conductive contacts include a plurality of solder pads spaced apart from each other, and are coupled to the electrode terminals, respectively. The stress generated by any one of the electrode terminals is distributed to all of the solder pads so as to prevent the electronic component from being offset during an assembly process.

公开(公告)号：US20170309534A1

公开(公告)日：2017-10-26

申请号：US15646695

申请日：2017-07-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Chang-Lun Lu ,  Shih-Ching Chen

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/16 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/18162

Abstract: An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.

公开(公告)号：US09601403B2

公开(公告)日：2017-03-21

申请号：US14982276

申请日：2015-12-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Guang-Hwa Ma ,  Shih-Ching Chen ,  Chang-Lun Lu

IPC: H01L27/32 ,  H01L23/31 ,  H01L25/16 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/3128 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/45099

Abstract: An electronic package is provided, which includes: a first circuit structure; at least first electronic element disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; a first encapsulant encapsulating the first electronic element and the first conductive element; and a second circuit structure formed on the first encapsulant and electrically connected to the first conductive element. By directly disposing the electronic element having high I/O functionality on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package. The invention further provides a method for fabricating the electronic package.

公开(公告)号：US20160066406A1

公开(公告)日：2016-03-03

申请号：US14516010

申请日：2014-10-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lu-Yi Chen ,  Chang-Lun Lu ,  Shih-Ching Chen

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/10 ,  H05K3/46 ,  H05K3/30 ,  B05D3/12 ,  H05K1/18

CPC classification number: H01L23/16 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/18162

Abstract: An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.

Abstract translation: 提供一种电子模块，包括电子元件和形成在电子元件的侧表面上但未形成在电子元件的有效表面上的加强层，以便加强电子模块的结构。 因此，当拾取和放置电子模块时，防止电子元件被损坏。

公开(公告)号：US20130252383A1

公开(公告)日：2013-09-26

申请号：US13628582

申请日：2012-09-27

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Lu-Yi Chen

IPC: H01L21/56 ,  H01L21/60

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/568 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

Abstract: A fabrication method of a wafer level semiconductor package includes: forming on a carrier a first dielectric layer having first openings exposing portions of the carrier; forming a circuit layer on the first dielectric layer, a portion of the circuit layer being formed in the first openings; forming on the first dielectric layer and the circuit layer a second dielectric layer having second openings exposing portions of the circuit layer; forming conductive bumps in the second openings; mounting a semiconductor component on the conductive bumps; forming an encapsulant for encapsulating the semiconductor component; and removing the carrier to expose the circuit layer. By detecting the yield rate of the circuit layer before mounting the semiconductor component, the invention avoids discarding good semiconductor components together with packages as occurs in the prior art, thereby saving the fabrication cost and improving the product yield.

Abstract translation: 晶片级半导体封装的制造方法包括：在载体上形成具有暴露载体部分的第一开口的第一介电层; 在所述第一电介质层上形成电路层，所述电路层的一部分形成在所述第一开口中; 在所述第一电介质层和所述电路层上形成具有暴露所述电路层的部分的第二开口的第二电介质层; 在所述第二开口中形成导电凸块; 将半导体部件安装在导电凸块上; 形成用于封装半导体部件的密封剂; 并移除载体以露出电路层。 通过在安装半导体部件之前检测电路层的成品率，本发明避免与现有技术中发生的封装一起丢弃良好的半导体部件，从而节省制造成本并提高产品产量。