公开(公告)号：US11848271B2

公开(公告)日：2023-12-19

申请号：US17366575

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chen-Hua Yu

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/24147 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20230395588A1

公开(公告)日：2023-12-07

申请号：US18447655

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L25/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L23/58 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/12

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/585 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L21/56 ,  H01L21/76838 ,  H01L23/12 ,  H01L23/562 ,  H01L24/06 ,  H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2225/06568 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US11817445B2

公开(公告)日：2023-11-14

申请号：US17687911

申请日：2022-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L21/44 ,  H01L25/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L23/58 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/12 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/85399

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US20230238306A1

公开(公告)日：2023-07-27

申请号：US18194792

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L21/76898 ,  H01L24/03 ,  H01L2224/05647 ,  H01L2224/02381 ,  H01L2224/08146 ,  H01L2224/0557 ,  H01L2224/05569 ,  H01L2224/02372 ,  H01L2224/02311

Abstract: A semiconductor device includes a first passivation layer over a circuit and. conductive pad over the first passivation layer, wherein the conductive pad is electrically connected to the circuit. A second passivation layer is disposed over the conductive pad and the first passivation layer, and has a first opening and a second opening. The first opening exposes an upper surface of a layer that extends underneath the conductive pad, and the second opening exposes the conductive pad. A first insulating layer is disposed over the second passivation layer and filling the first and second openings. A through substrate via extends through the insulating layer, second passivation layer, passivation layer, and substrate. A side of the through substrate via and the second passivation layer have a gap that is filled with the first insulating layer. A conductive via extends through the first insulating layer and connecting to the conductive pad.

公开(公告)号：US11676939B2

公开(公告)日：2023-06-13

申请号：US17140835

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/78 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/18162 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/83005

Abstract: A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.

公开(公告)号：US11557581B2

公开(公告)日：2023-01-17

申请号：US16882759

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00

Abstract: A method is provided. A bottom tier package structure is bonded to a support substrate through a first bonding structure, wherein the bottom tier package structure includes a first semiconductor die encapsulated by a first insulating encapsulation, and the first bonding structure includes stacked first dielectric layers and at least one stacked first conductive features penetrating through the stacked first dielectric layers. The support substrate is placed on a grounded stage such that the first semiconductor die is grounded through the at least one first stacked conductive features, the support substrate and the grounded stage. A second semiconductor die is bonded to the bottom tier package structure through a second bonding structure, wherein the second bonding structure includes stacked second dielectric layers and at least one stacked second conductive features penetrating through the stacked second dielectric layers. The second semiconductor die is encapsulated with a second insulating encapsulation.

公开(公告)号：US11417587B2

公开(公告)日：2022-08-16

申请号：US16856044

申请日：2020-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. The first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. The bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. The second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. The second insulating encapsulation laterally encapsulates the second semiconductor die.

公开(公告)号：US11309243B2

公开(公告)日：2022-04-19

申请号：US16929118

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Sen-Bor Jan

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package has a first region and a second region. The package includes a first die, a second die, an encapsulant, and an inductor. The second die is stacked on and bonded to the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. A metal density in the first region is greater than a metal density in the second region.

公开(公告)号：US11257791B2

公开(公告)日：2022-02-22

申请号：US16876108

申请日：2020-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00 ,  H01L23/00

Abstract: A stacked die structure includes a base die, a top die and conductive terminals electrically connected to the top die. The base die includes a base semiconductor substrate, a base interconnection layer disposed on the base semiconductor substrate, and a base bonding layer disposed on the base interconnection layer. The top die is stacked on the base die and electrically connected to the base die, wherein the top die includes a top bonding layer, a top semiconductor substrate, a top interconnection layer, top conductive pads and top grounding vias. The top bonding layer is hybrid bonded to the base bonding layer. The top interconnection layer is disposed on the top semiconductor substrate and includes a dielectric layer, conductive layers embedded in the dielectric layer, and conductive vias joining the conductive layers. The conductive pads and top grounding vias are embedded in the dielectric layer and disposed on the conductive layers.

公开(公告)号：US20210364710A1

公开(公告)日：2021-11-25

申请号：US16877498

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: G02B6/42 ,  H01L23/498 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor die, a device layer, an insulator layer, a buffer layer, and connective terminals. The device layer is stacked over the semiconductor die. The device layer includes an edge coupler located at an edge of the semiconductor package and a waveguide connected to the edge coupler. The insulator layer is stacked over the device layer and includes a first dielectric material. The buffer layer is stacked over the insulator layer. The buffer layer includes a second dielectric material. The connective terminals are disposed on the buffer layer and reach the insulator layer through contact openings of the buffer layer.