公开(公告)号：US09536888B2

公开(公告)日：2017-01-03

申请号：US14580505

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Harry-Hak-Lay Chuang ,  Shih-Chang Liu

IPC: H01L31/112 ,  H01L27/108 ,  H01L29/00 ,  H01L31/036 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548

Abstract: The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region. A first plurality of dielectric bodies are formed within the first plurality of openings and a second plurality of dielectric bodies are formed within the second plurality of openings. A second masking layer is formed over the first masking layer and the first and second plurality of dielectric bodies. The first and second masking layers are removed at the memory cell region, and a first conductive layer is formed to fill recesses between the first plurality of dielectric bodies. A planarization process reduces a height of the first conductive layer and removes the first conductive layer from over the boundary region.

Abstract translation: 本公开涉及一种形成集成电路的方法。 在一些实施例中，该方法通过在衬底上图案化第一掩模层来进行，以在存储单元区域处具有第一多个开口，并在边界区域具有第二多个开口。 在所述第一多个开口内形成有第一多个介电体，并且在所述第二多个开口内形成第二多个介电体。 在第一掩蔽层和第一和第二多个电介质体之上形成第二掩模层。 在存储单元区域处去除第一和第二掩模层，并且形成第一导电层以填充第一多个电介质体之间的凹部。 平坦化处理降低了第一导电层的高度，并从边界区域上移除第一导电层。

公开(公告)号：US20160379987A1

公开(公告)日：2016-12-29

申请号：US14749970

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Yu-Hsing Chang ,  Yuan-Tai Tseng

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/11524 ,  H01L27/11534 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/7851

Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Abstract translation: 本公开涉及具有FinFET器件和嵌入式闪存器件的集成芯片及其形成方法。 在一些实施例中，集成芯片具有与逻辑区域横向分离的逻辑区域和存储区域。 逻辑区域具有从半导体衬底向外突出的半导体材料的第一多个翅片。 栅电极设置在半导体材料的第一多个散热片上。 存储区域具有从半导体衬底向外延伸的第二多个半导体材料翅片。 嵌入式闪存单元被布置在半导体材料的第二多个鳍上。 所得到的集成芯片结构提供了良好的性能，因为它包含FinFET器件和嵌入式闪存器件。

公开(公告)号：US20160351806A1

公开(公告)日：2016-12-01

申请号：US15233028

申请日：2016-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Pei Hsieh ,  Chung-Yen Chou ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1691 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/149 ,  H01L45/1675

Abstract: The present disclosure relates to an integrated circuit device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a bottom electrode disposed over a lower metal interconnect layer. The integrated circuit device also has a resistance switching layer with a variable resistance located on the bottom electrode, and a top electrode located over the resistance switching layer. The integrated circuit device also has a self-sputtering spacer having a lateral portion that surrounds the bottom electrode at a position that is vertically disposed between the resistance switching layer and a bottom etch stop layer and a vertical portion abutting sidewalls of the resistance switching layer and the top electrode. The integrated circuit device also has a top etch stop layer located over the bottom etch stop layer abutting sidewalls of the self-sputtering spacer and overlying the top electrode.

Abstract translation: 本公开涉及具有RRAM单元的集成电路器件及其相关联的形成方法。 在一些实施例中，集成电路器件具有设置在下金属互连层上的底电极。 集成电路器件还具有位于底部电极上的具有可变电阻的电阻切换层，以及位于电阻切换层上方的顶部电极。 集成电路器件还具有自溅射间隔物，该自溅射间隔物具有侧垂部分，该侧向部分在垂直设置在电阻切换层和底部蚀刻停止层之间的位置和邻接电阻切换层侧壁的垂直部分之间包围底部电极;以及 顶部电极。 集成电路器件还具有位于底部蚀刻停止层上方的顶部蚀刻停止层，其邻接自溅射间隔物的侧壁并且覆盖顶部电极。

公开(公告)号：US09484351B2

公开(公告)日：2016-11-01

申请号：US14182952

申请日：2014-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L29/42344 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/42348 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a split gate memory device which requires less number of processing steps than traditional baseline processes and methods of making the same. Word gate/select gate (SG) pairs are formed around a sacrificial spacer. The resulting SG structure has a distinguishable non-planar top surface. The spacer layer that covers the select gate also follows the shape of the SG top surface. A dielectric disposed above the inter-gate dielectric layer and arranged between the neighboring sidewalls of the each memory gate and select gate provides isolation between them.

Abstract translation: 本公开涉及一种分裂门存储器件，其需要比传统的基线工艺更少数量的处理步骤及其制造方法。 字栅/选择栅极（SG）对围绕牺牲间隔物形成。 所得到的SG结构具有可区分的非平面顶表面。 覆盖选择栅的间隔层也遵循SG顶表面的形状。 设置在栅极间介电层上方并且布置在每个存储器栅极和选择栅极的相邻侧壁之间的电介质在它们之间提供隔离。

公开(公告)号：US20160043306A1

公开(公告)日：2016-02-11

申请号：US14918671

申请日：2015-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

Abstract translation: 集成电路器件包括衬底和磁隧道结（MTJ）。 MTJ至少包括钉扎层，阻挡层和自由层。 MTJ形成在衬底的表面上。 在被钉扎层，阻挡层和自由层中，自由层首先形成并且最接近表面。 这使得在蚀刻自由层之前，可以在自由层的周边区域上形成间隔物。 由蚀刻或其它自由层边界限定工艺导致的对自由层的任何损伤通过间隔物保持与隧道结一定距离。

公开(公告)号：US09209392B1

公开(公告)日：2015-12-08

申请号：US14513781

申请日：2014-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L45/08 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for efficient switching of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode surrounded by a spacer and a bottom dielectric layer. The bottom electrode, the spacer, and the bottom dielectric layer are disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the spacer narrows the later formed bottom electrode, thereby improving switch efficiency of the RRAM cell.

Abstract translation: 本公开涉及具有提供RRAM单元的有效切换的底部电极的电阻随机存取存储器（RRAM）单元以及相关联的形成方法。 在一些实施例中，RRAM单元具有由间隔物和底部电介质层包围的底部电极。 底部电极，间隔物和底部电介质层设置在由下部电介质层（ILD）层围绕的下部金属互连层上。 具有可变电阻的电介质数据存储层位于底部电介质层和底部电极之上，并且顶部电极设置在电介质数据存储层上。 间隔物的放置使后面形成的底部电极变窄，从而提高RRAM电池的开关效率。

公开(公告)号：US20150279849A1

公开(公告)日：2015-10-01

申请号：US14225874

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.

Abstract translation: 一些实施例涉及具有纳米晶体的电荷捕获层的存储器单元，其包括沿着选择栅极的隧穿氧化物层，形成在控制栅极和隧道氧化物层之间的控制氧化物层，以及多个纳米晶体，其布置在隧道 并控制氧化物层。 封装层将纳米晶体与控制氧化物层隔离。 与选择栅极的接触形成包括两步蚀刻。 第一蚀刻包括氧化物和封装层之间的选择性，并且蚀刻掉控制氧化物层，同时保持封装层完好无损。 具有与第一蚀刻相反的选择性的第二蚀刻然后在完全留下隧道氧化物层的同时蚀刻封装层。 结果，将控制氧化物层和纳米晶体从选择栅极的表面蚀刻掉，同时使隧道氧化物层完好无损以进行接触隔离。

公开(公告)号：US20150255718A1

公开(公告)日：2015-09-10

申请号：US14196361

申请日：2014-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00

CPC classification number: H01L45/1691 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

Abstract translation: 本公开涉及一种电阻随机存取存储器（RRAM）器件架构，其包括在RRAM单元的下部金属互连和底部电极之间的导电蚀刻停止层的薄单层。 导电蚀刻停止层提供了结构的简单性，并且该层的蚀刻选择性为下层提供了保护。 可以使用干式或湿式蚀刻来蚀刻导电蚀刻停止层以落在下部金属互连上。 在下金属互连是铜的情况下，蚀刻导电蚀刻停止层以露出铜不会像传统方法那样产生尽可能多的非挥发性铜蚀刻副产物。 与传统方法相比，所公开的技术的一些实施例减少了掩模步骤的数量，并且还减少了在形成底部电极期间的化学机械抛光。

公开(公告)号：US09048316B2

公开(公告)日：2015-06-02

申请号：US14013653

申请日：2013-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Fu-Ting Sung ,  Chung-Chiang Min ,  Wei-Hang Huang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L27/115 ,  G11C16/16 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76805 ,  H01L23/528 ,  H01L27/11521 ,  H01L29/34 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°.

Abstract translation: 提供半导体器件结构的机构的实施例。 半导体器件结构包括衬底和设置在衬底上的字线单元。 半导体器件还包括设置在衬底上并与字线单元相邻并且在存储器栅极的侧壁上的间隔物的存储器栅极。 间隔物和字线单元位于存储器栅极的相对侧。 此外，存储器栅极的顶表面和存储器栅极的侧壁之间的角度在约75°至约90°的范围内。

公开(公告)号：US08853768B1

公开(公告)日：2014-10-07

申请号：US13798393

申请日：2013-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Tsung-Hsueh Yang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L29/792 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/7881

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate structures having asymmetric sidewalls including a tall side and a short side. Adjacent ones of the plurality of gate structures are separated by a tall side-tall side region and a short side-short side region. The method further comprises forming a spacer layer over the plurality of gate structures and a bottom surface of the tall side-tall side region and the short side-short side region, depositing an oxide layer over the spacer layer, etching the bottom surface portions of the oxide layer, and selectively etching the sidewall portions of the oxide layer in the tall side-tall side region.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括形成具有包括高边和短边的不对称侧壁的多个栅极结构。 多个栅极结构中的相邻的栅极结构被一个高的侧边侧区域和短侧边区域隔开。 所述方法还包括在所述多个栅极结构上形成间隔层，以及在所述高侧边侧区域和所述短边侧短边区域的底表面上形成间隔层，在所述间隔层上方沉积氧化物层， 氧化物层，并且选择性地蚀刻位于高侧高侧区域中的氧化物层的侧壁部分。