公开(公告)号：US20180165397A1

公开(公告)日：2018-06-14

申请号：US15379084

申请日：2016-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Shuo-Yen Chou ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/06

Abstract: Target optimization methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an IC design layout for a target pattern, wherein the target pattern has a corresponding target contour; modifying the target pattern, wherein the modified target pattern has a corresponding modified target contour; and generating an optimized target pattern when the modified target contour achieves functionality of the target pattern as defined by a constraint layer. The method can further include defining a cost function based on the constraint layer, where the cost function correlates a spatial relationship between a contour of the target pattern and the constraint layer.

公开(公告)号：US20180090370A1

公开(公告)日：2018-03-29

申请号：US15395310

申请日：2016-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Cheng Hung ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ta-Ching Yu ,  Yung-Sung Yen ,  Ziwei Fang ,  Tsai-Sheng Gau ,  Chin-Hsiang Lin ,  Kuei-Shun Chen

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/31155

Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects.

公开(公告)号：US20180019207A1

公开(公告)日：2018-01-18

申请号：US15714172

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Peng ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Yung-Sung Yen

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L21/76816 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/00

Abstract: In some embodiments, the present disclosure relates to an integrated chip having a lower power rail continuously extending over a plurality of gate structures. A first set of connection pins straddle a first edge of the lower power rail, and a second set of connection pins straddle a second edge of the lower power rail, which is opposite the first edge. The first set of connection pins and the second set of connection pins are electrically coupled to the lower power rail. An upper power rail is over the lower power rail and is electrically coupled to the first set of connection pins and the second set of connection pins. The first set of connection pins are arranged at a first pitch and the second set of connection pins arranged with respect to the first set of connection pins at a second pitch less than the first pitch.

公开(公告)号：US20170338146A1

公开(公告)日：2017-11-23

申请号：US15593149

申请日：2017-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Sung Yen ,  Yu-Hsun Chen ,  Chen-Hau Wu ,  Chun-Kuang Chen ,  Ta-Ching Yu ,  Ken-Hsien Hsieh ,  Ming-Jhih Kuo ,  Ru-Gun Liu

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L23/528 ,  H01L23/5283

Abstract: Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.

公开(公告)号：US20170323832A1

公开(公告)日：2017-11-09

申请号：US15148274

申请日：2016-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Yang ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Meng-Hung Shen ,  Ru-Gun Liu ,  Wei-Cheng Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/823437 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/785

Abstract: The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance.

公开(公告)号：US20170317027A1

公开(公告)日：2017-11-02

申请号：US15143842

申请日：2016-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Charles Chew-Yuen Young ,  Chi-Yeh Yu ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Pin-Dai Sue ,  Ru-Gun Liu ,  Shi-Wei Peng ,  Wen-Hao Chen ,  Yung-Sung Yen ,  Chun-Kuang Chen

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/522 ,  H01L23/5222 ,  H01L27/0924

Abstract: The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a middle-end-of-the-line (MEOL) layer to a power rail. In some embodiments, the integrated chip has an active area with a plurality of source/drain regions. The active area contacts a MEOL structure extending in a first direction. A first metal wire extends in a second direction, which is perpendicular to the first direction, at a location overlying the MEOL structure. A metal strap extending in a first direction is arranged over the first metal wire. The metal strap is configured to connect the first metal line to a power rail (e.g., which may be held at a supply or ground voltage), which extends in the second direction. By connecting the MEOL structure to the power rail by way of a metal strap, parasitic capacitance and electromigration may be reduced.

公开(公告)号：US20170316938A1

公开(公告)日：2017-11-02

申请号：US15267341

申请日：2016-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ping Chiang ,  Ya-Ting Chang ,  Wen-Li Cheng ,  Nian-Fuh Cheng ,  Ming-Hui Chih ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: H01L21/033 ,  G03F7/20

CPC classification number: G03F7/70283 ,  G03F1/70 ,  G06F17/5081 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76831 ,  H01L21/76843 ,  H01L31/1892

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.

公开(公告)号：US09799529B2

公开(公告)日：2017-10-24

申请号：US15072792

申请日：2016-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Sung Yen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Hsin-Chih Chen

IPC: H01L21/3105 ,  H01L21/8234

CPC classification number: H01L21/31055 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first flowable-material (FM) layer over a substrate. A top surface of the first FM layer in a first region is higher than a top surface of the first FM layer in a second region. The method also includes forming a sacrificial plug to cover the first FM layer in the first region, forming a second FM layer over the sacrificial plug in the first region and over the first FM layer in the second region, performing a first recessing process such that the second FM layer is removed in the first region and performing a second recessing process on the second FM layer in the second region while the first FM layer is protected by the sacrificial plug in the first region.

公开(公告)号：US09684236B1

公开(公告)日：2017-06-20

申请号：US15073073

申请日：2016-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Hsien Hsieh ,  Kuan-Hsin Lo ,  Shih-Ming Chang ,  Wei-Liang Lin ,  Joy Cheng ,  Chun-Kuang Chen ,  Ching-Yu Chang ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Chin-Hsiang Lin

IPC: G03F7/11 ,  G03F7/40 ,  G03F7/00 ,  H01L21/308 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3213 ,  G03F7/20 ,  G03F7/16 ,  G03F7/32 ,  H01L21/027 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3065

CPC classification number: G03F7/002 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/165 ,  G03F7/20 ,  G03F7/2022 ,  G03F7/2059 ,  G03F7/32 ,  G03F7/40 ,  H01L21/02112 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3086

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first patterned hard mask over a material layer. The first patterned hard mask defines an opening. The method also includes forming a direct-self-assembly (DSA) layer having a first portion and a second portion within the opening, removing the first portion of the DSA layer, forming spacers along sidewalls of the second portion of the DSA layer and removing the second portion of the DSA layer. The spacers form a second patterned hard mask over the material layer.

公开(公告)号：US09026955B1

公开(公告)日：2015-05-05

申请号：US14051568

申请日：2013-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Feng-Ju Chang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F7/70433 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

Abstract translation: 本公开涉及通过分开校正IC设计的主要特征形状和虚拟形状以及相关联的装置来减少图案校正周期时间的集成芯片（IC）设计图案校正的方法。 在一些实施例中，通过形成具有多个主要特征形状的IC设计来执行该方法。 将多个虚拟形状添加到IC设计中以改善IC设计的处理窗口。 使用第一图案校正处理来校正多个主要特征形状。 随后使用与第一图案校正处理分开的第二图案校正处理来校正多个虚拟形状中的一个或多个。 通过单独地校正虚拟形状和主要特征形状，可以对虚拟形状进行具有较低时间/资源需求的不同的图案校正处理，从而减少图案校正周期时间。