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    Method of manufacturing semiconductor device with silicide
    32.
    发明授权
    Method of manufacturing semiconductor device with silicide 有权
    用硅化物制造半导体器件的方法

    公开(公告)号：US08476164B1

    公开(公告)日：2013-07-02

    申请号：US13661111

    申请日：2012-10-26

    Applicant: United Microelectronics Corp.

    Inventor： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chih-Chien Liu ,  Chia-Lin Hsu ,  Chun-Yuan Wu

    IPC: H01L21/44

    CPC classification number: H01L29/665 ,  H01L29/78 ,  H01L29/7845

    Abstract: A method of manufacturing semiconductor device is provided. A substrate at least with a patterned silicon-containing layer on the substrate and spacers adjacent to the patterned silicon-containing layer is provided. A metal layer is formed on the substrate and covers the patterned silicon-containing layer and spacers. Then, a capping layer is formed on the metal layer. A first rapid thermal process is performed to at least make a portion of the metal layer react with the substrate around the spacers to form transitional silicides. The capping layer and the unreacted portions of the metal layer are removed. A first nitride film with a first tensile stress S1 is formed on the substrate. A second rapid thermal process is performed to transfer the transitional silicide to a silicide and transfer the first nitride film to a second nitride film with a second tensile stress S2, wherein S2>S1.

    Abstract translation: 提供一种制造半导体器件的方法。 提供至少在衬底上具有图案化的含硅层的衬底和与图案化的含硅层相邻的衬垫。 在基板上形成金属层，并覆盖图案化的含硅层和间隔物。 然后，在金属层上形成覆盖层。 进行第一快速热处理以至少使金属层的一部分与衬垫周围的衬底反应以形成过渡的硅化物。 除去覆盖层和金属层的未反应部分。 在基板上形成具有第一拉伸应力S1的第一氮化物膜。 执行第二快速热处理以将过渡硅化物转移到硅化物，并将第一氮化物膜转移到具有第二拉伸应力S2的第二氮化物膜，其中S2> S1。

    SEMICONDUCTOR DEVICE HAVING STRAINED FIN STRUCTURE AND METHOD OF MAKING THE SAME
    35.
    发明申请
    SEMICONDUCTOR DEVICE HAVING STRAINED FIN STRUCTURE AND METHOD OF MAKING THE SAME 有权
    具有应变熔体结构的半导体器件及其制造方法

    公开(公告)号：US20150348971A1

    公开(公告)日：2015-12-03

    申请号：US14825165

    申请日：2015-08-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165

    CPC classification number: H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

    Abstract translation: 半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。 半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。 与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。 第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。

    Gradient dopant of strained substrate manufacturing method of semiconductor device
    37.
    发明授权
    Gradient dopant of strained substrate manufacturing method of semiconductor device 有权
    半导体器件应变衬底制造方法的梯度掺杂剂

    公开(公告)号：US09064893B2

    公开(公告)日：2015-06-23

    申请号：US13892424

    申请日：2013-05-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chin-I Liao ,  Chin-Cheng Chien

    IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02

    CPC classification number: H01L29/66636 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66795

    Abstract: A manufacturing method of a semiconductor device is provided. The method includes at least the following steps. A gate structure is formed on a substrate. An epitaxial structure is formed on the substrate, wherein the epitaxial structure comprises SiGe, and the Ge concentration in the epitaxial structure is equal to or higher than 45%. A first cap layer is formed on the epitaxial structure, wherein the first cap layer comprises Si. The first cap layer is doped with boron for forming a flat top surface of the first cap layer.

    Abstract translation: 提供一种半导体器件的制造方法。 该方法至少包括以下步骤。 在基板上形成栅极结构。 在衬底上形成外延结构，其中外延结构包括SiGe，外延结构中的Ge浓度等于或高于45％。 第一盖层形成在外延结构上，其中第一盖层包括Si。 第一盖层掺杂有硼以形成第一盖层的平坦顶表面。

    Method of Manufacturing Semiconductor Device Having Metal Gate
    38.
    发明申请
    Method of Manufacturing Semiconductor Device Having Metal Gate 有权
    具有金属栅极的半导体器件的制造方法

    公开(公告)号：US20150079777A1

    公开(公告)日：2015-03-19

    申请号：US14029824

    申请日：2013-09-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ted Ming-Lang Guo ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chun-Yuan Wu

    IPC: H01L21/28

    CPC classification number: H01L21/28176 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.

    Abstract translation: 提供一种制造具有金属栅极的半导体器件的方法。 提供具有形成在其上的第一导电型晶体管和第二导电型晶体管的衬底。 第一导电型晶体管具有第一沟槽，第二导电型晶体管具有第二沟槽。 在第一沟槽中形成第一功函数层。 对第一功函数层进行硬化处理。 对第一功函数层的一部分进行软化处理。 执行拉回步骤以去除第一功函数层的部分。 在第二沟槽中形成第二功函数层。 在第一沟槽和第二沟槽中形成低电阻金属层。

    Epitaxial layer
    39.
    发明授权
    Epitaxial layer 有权
    外延层

    公开(公告)号：US08928126B2

    公开(公告)日：2015-01-06

    申请号：US13670476

    申请日：2012-11-07

    Applicant: United Microelectronics Corp.

    Inventor： Chin-I Liao ,  Chin-Cheng Chien

    IPC: H01L21/02

    CPC classification number: H01L21/0262 ,  H01L21/0237 ,  H01L21/02576 ,  H01L21/02639 ,  H01L29/0843 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

    Abstract: A method of forming an epitaxial layer includes the following steps. At first, a first epitaxial growth process is performed to form a first epitaxial layer on a substrate, and a gas source of silicon, a gas source of carbon, a gas source of phosphorous and a gas source of germanium are introduced during the first epitaxial growth process to form the first epitaxial layer including silicon, carbon, phosphorous and germanium. Subsequently, a second epitaxial growth process is performed to form a second epitaxial layer, and a number of elements in the second epitaxial layer is smaller than a number of elements in the first epitaxial layer.

    Abstract translation: 形成外延层的方法包括以下步骤。 首先，执行第一外延生长工艺以在衬底上形成第一外延层，并且在第一外延期间引入硅气体源，碳气体源，磷气体源和锗气体源 生长工艺以形成包括硅，碳，磷和锗的第一外延层。 随后，进行第二外延生长工艺以形成第二外延层，并且第二外延层中的多个元件小于第一外延层中的元件的数量。

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