公开(公告)号：US20160190063A1

公开(公告)日：2016-06-30

申请号：US14983401

申请日：2015-12-29

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE ,  Ho-Yin YIU

IPC: H01L23/522 ,  H01L21/76 ,  H01L21/304 ,  H01L21/683 ,  H01L21/268 ,  H01L21/768 ,  H01L23/528 ,  H01L21/78

CPC classification number: H01L24/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/31127 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14678 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/0311 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

公开(公告)号：US20160133544A1

公开(公告)日：2016-05-12

申请号：US14869602

申请日：2015-09-29

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN ,  Shih-Yi LEE ,  Ho-Yin YIU

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31 ,  H01L21/78 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/00 ,  H01L21/268

CPC classification number: H01L21/76898 ,  H01L21/2633 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/43 ,  H01L24/45 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0233 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06135 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/432 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

Abstract translation: 芯片封装包括芯片，激光器停止器，隔离层，再分布层，绝缘层和导电结构。 芯片具有导电焊盘，第一表面和与第一表面相对的第二表面。 导电垫位于第一表面上。 第二表面具有第一通孔以暴露导电垫。 激光停止器位于导电垫上。 隔离层位于第二表面和第一通孔中。 隔离层具有与第二表面相对的第三表面。 隔离层和导电垫在一起具有第二通孔，使得激光阻挡件通过第二通孔露出。 再分配层位于第三表面，第二通孔的侧壁和激光停止器上。

公开(公告)号：US20150303178A1

公开(公告)日：2015-10-22

申请号：US14692613

申请日：2015-04-21

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/04

CPC classification number: H01L25/16 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/45101 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73209 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19105 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/206

Abstract: A chip package includes a semiconductor chip, a first chip, a first connection portion, a molding layer, a metal redistribution layer and a packaging layer. The semiconductor chip includes a first conductive pad and a second conductive pad disposed on an upper surface of the semiconductor chip. The first chip is disposed on the upper surface, and the first chip has at least a first chip conductive pad. The first connection portion directly electrically connects the first chip conductive pad and the first conductive pad. The molding layer covers the upper surface, the first chip and the first connection portion, and the molding layer is formed with an opening exposing a second conductive pad. The metal redistribution layer is disposed in the opening, electrically connected to the second conductive pad and extending to the molding layer. The packaging layer covers the metal redistribution layer and the molding layer.

Abstract translation: 芯片封装包括半导体芯片，第一芯片，第一连接部分，成型层，金属再分配层和封装层。 半导体芯片包括设置在半导体芯片的上表面上的第一导电焊盘和第二导电焊盘。 第一芯片设置在上表面上，并且第一芯片具有至少第一芯片导电焊盘。 第一连接部分直接电连接第一芯片导电焊盘和第一导电焊盘。 模制层覆盖上表面，第一芯片和第一连接部分，并且模制层形成有露出第二导电焊盘的开口。 金属再分配层设置在开口中，电连接到第二导电垫并延伸到模制层。 包装层覆盖金属再分配层和成型层。

公开(公告)号：US20150255499A1

公开(公告)日：2015-09-10

申请号：US14621240

申请日：2015-02-12

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Chia-Ming CHENG ,  Chien-Hung LIU

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14605 ,  H01L27/14621 ,  H01L27/14685 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A chip package includes a semiconductor chip, insulation layer, redistribution layer and packaging layer and is formed with a cavity. The semiconductor chip has an electronic component and a conductive pad. The conductive pad and the electronic component are disposed on an upper surface of the semiconductor chip and electrically connected. The cavity opens from a lower surface of the semiconductor chip and tapers toward the upper surface to expose the conductive pad. The insulation layer coats the lower surface and a portion of the cavity. The insulation layer is formed with a gap to expose the conductive pad. The redistribution layer coats the lower surface and a portion of the cavity and is electrically connected to the conductive pad through the gap. The packaging layer coats the lower surface and a portion of the cavity.

Abstract translation: 芯片封装包括半导体芯片，绝缘层，再分配层和封装层，并且形成有空腔。 半导体芯片具有电子部件和导电焊盘。 导电焊盘和电子部件设置在半导体芯片的上表面上并电连接。 该空腔从半导体芯片的下表面开口并朝向上表面逐渐变细以暴露导电垫。 绝缘层涂覆下表面和空腔的一部分。 绝缘层形成有间隙以暴露导电垫。 再分布层包覆下表面和空腔的一部分，并通过间隙电连接到导电垫。 包装层涂覆下表面和空腔的一部分。

公开(公告)号：US20150145094A1

公开(公告)日：2015-05-28

申请号：US14552186

申请日：2014-11-24

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/146 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/24051 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/8385 ,  H01L2224/92133 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14335 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads.

Abstract translation: 提供了包括第一基板的芯片封装。 多个第一导电焊盘设置在第一基板的第一侧上。 第二基板附接到与第一基板的第一侧相对的第二侧。 第二基板包括微电元件，并且具有多个与多个第一导电焊盘相对应的第二导电焊盘，该第二导电焊盘设置在第二基板的第一侧上且位于第一基板和第二基板之间。 再分配层设置在与第二基板的第一侧相对的第二侧上。 再分配层穿透第二基板，第二导电焊盘和第一基板并延伸到第一导电焊盘中以电连接第一和第二导电焊盘。

公开(公告)号：US20140225237A1

公开(公告)日：2014-08-14

申请号：US14172832

申请日：2014-02-04

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L21/78 ,  B81B7/0064 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/11 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A chip scale package structure includes a chip, a dam unit, a board body, a plurality of first conductors, an encapsulating glue, a plurality of first conductive layers, an isolation layer, and a plurality of first electrodes. The dam unit is disposed on the surface of the chip. The board body is located on the dam unit. The first conductors are respectively in electrical contact with the conductive pads of the chip. The encapsulating glue covers the surface of the chip, and the board body and the first conductors are packaged in the encapsulating glue. The first conductive layers are located on the surface of the encapsulating glue opposite to the chip and respectively in electrical contact with the first conductors. The isolation layer is located on the encapsulating glue and the first conductive layers. The first electrodes are respectively in electrical contact with the first conductive layers.

Abstract translation: 芯片级封装结构包括芯片，堤坝单元，板体，多个第一导体，封装胶，多个第一导电层，隔离层和多个第一电极。 大坝单元设置在芯片的表面上。 板体位于坝体上。 第一导体分别与芯片的导电焊盘电接触。 封装胶覆盖芯片的表面，并且板体和第一导体封装在封装胶中。 第一导电层位于与芯片相对的封装胶的表面上，分别与第一导体电接触。 隔离层位于封装胶和第一导电层上。 第一电极分别与第一导电层电接触。