公开(公告)号：US20050042889A1

公开(公告)日：2005-02-24

申请号：US10888110

申请日：2004-07-09

申请人： Albert Lee ,  Annamalai Lakshmanan ,  Bok Kim ,  Li-Qun Xia ,  Mei-Yee Shek

发明人： Albert Lee ,  Annamalai Lakshmanan ,  Bok Kim ,  Li-Qun Xia ,  Mei-Yee Shek

IPC分类号： C23C16/30 ,  C23C16/40 ,  C23C16/56 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/31 ,  H01L21/336 ,  H01L21/469

CPC分类号： C23C16/30 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834

摘要： Methods and apparatus are provided for processing a substrate with a bilayer barrier layer. In one aspect, the invention provides a method for processing a substrate including depositing a nitrogen containing barrier layer on a substrate surface and then depositing a nitrogen free barrier layer thereon. The barrier layer may be deposited over dielectric materials, conductive materials, or both. The bilayer barrier layer may also be used as an etch stop, an anti-reflective coating, or a passivation layer.

摘要翻译： 提供了用于处理具有双层阻挡层的衬底的方法和装置。 一方面，本发明提供了一种处理衬底的方法，包括在衬底表面上沉积含氮阻挡层，然后在其上沉积无氮阻挡层。 阻挡层可以沉积在电介质材料，导电材料或两者上。 双层阻挡层也可以用作蚀刻停止层，抗反射涂层或钝化层。

公开(公告)号：US08481422B2

公开(公告)日：2013-07-09

申请号：US13455299

申请日：2012-04-25

申请人： Kelvin Chan ,  Khaled A. Elsheref ,  Alexandros T. Demos ,  Mei-Yee Shek ,  Lipan Li ,  Li-Qun Xia ,  Kang Sub Yim

发明人： Kelvin Chan ,  Khaled A. Elsheref ,  Alexandros T. Demos ,  Mei-Yee Shek ,  Lipan Li ,  Li-Qun Xia ,  Kang Sub Yim

IPC分类号： H01L21/4763

CPC分类号： H01L21/3141 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31608 ,  H01L21/76814 ,  H01L21/76831

摘要： A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch.

摘要翻译： 提供了一种处理基板的方法和装置。 在基板上形成多孔介电层。 在一些实施例中，电介质可以由致密的电介质层封盖。 对电介质层进行图案化，并且将致密的电介质层保形地沉积在衬底上。 密实的保形介电层密封多孔介电层的孔隙，防止与可能渗入孔隙的物质接触。 通过方向选择性蚀刻去除覆盖图案开口的场区域和底部的稠密共形孔隙电介质层的部分。

公开(公告)号：US07566655B2

公开(公告)日：2009-07-28

申请号：US11398436

申请日：2006-04-05

申请人： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

发明人： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

IPC分类号： H01L21/44

CPC分类号： H01L29/7843 ,  C23C16/345 ,  C23C16/56 ,  H01L21/28044 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/66583

摘要： A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.

摘要翻译： 工艺流程集成方案采用一种或多种技术来控制由此形成的半导体器件中的应力。 根据一个实施例，由氮化物间隔物和多晶硅栅极的RTP贡献的累积应力以及随后沉积高应力蚀刻停止层，增强应变并提高器件性能。 可以将锗沉积或植入栅极结构中以便于应力控制。

公开(公告)号：US20080020591A1

公开(公告)日：2008-01-24

申请号：US11762590

申请日：2007-06-13

申请人： Mihaela Balseanu ,  Victor Nguyen ,  Li-Qun Xia ,  Derek Witty ,  Hichem M'Saad ,  Mei-Yee Shek ,  Isabelita Roflox

发明人： Mihaela Balseanu ,  Victor Nguyen ,  Li-Qun Xia ,  Derek Witty ,  Hichem M'Saad ,  Mei-Yee Shek ,  Isabelita Roflox

IPC分类号： H01L21/31

CPC分类号： H01L21/3105 ,  C23C16/345 ,  C23C16/56 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/66583 ,  H01L29/7843

摘要： Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for improved performance of the underlying MOS transistor device. In accordance with alternative embodiments, a deposited silicon nitride film is exposed to curing with ultraviolet (UV) radiation at an elevated temperature, thereby helping remove hydrogen from the film and increasing film stress. In accordance with still other embodiments, a silicon nitride film is formed utilizing an integrated process employing a number of deposition/curing cycles to preserve integrity of the film at the sharp corner of the underlying raised feature. Adhesion between successive layers may be promoted by inclusion of a post-UV cure plasma treatment in each cycle.

摘要翻译： 氮化硅层的应力可以通过在较高温度下沉积来增强。 使用允许将衬底加热到​​基本上大于400℃的装置（例如由陶瓷而不是铝制成的加热器），沉积的氮化硅膜可能表现出增强的应力，从而可以改善下面的MOS晶体管的性能 设备。 根据替代实施例，沉积的氮化硅膜在升高的温度下暴露于紫外线（UV）辐射固化，从而有助于从膜中除去氢并增加膜应力。 根据其他实施例，使用采用多个沉积/固化周期的整合方法形成氮化硅膜，以保持薄膜在底层凸起特征的尖角处的完整性。 可以通过在每个循环中包括UV后固化等离子体处理来促进连续层之间的粘附。

公开(公告)号：US08445075B2

公开(公告)日：2013-05-21

申请号：US12975833

申请日：2010-12-22

申请人： Huiwen Xu ,  Mei-Yee Shek ,  Li-Qun Xia ,  Amir Al-Bayati ,  Derek Witty ,  Hichem M'Saad

发明人： Huiwen Xu ,  Mei-Yee Shek ,  Li-Qun Xia ,  Amir Al-Bayati ,  Derek Witty ,  Hichem M'Saad

IPC分类号： B05D3/10

CPC分类号： C23C16/308 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3122 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834

摘要： Methods of processing films on substrates are provided. In one aspect, the methods comprise treating a patterned low dielectric constant film after a photoresist is removed from the film by depositing a thin layer comprising silicon, carbon, and optionally oxygen and/or nitrogen on the film. The thin layer provides a carbon-rich, hydrophobic surface for the patterned low dielectric constant film. The thin layer also protects the low dielectric constant film from subsequent wet cleaning processes and penetration by precursors for layers that are subsequently deposited on the low dielectric constant film.

摘要翻译： 提供了在基板上处理膜的方法。 在一个方面，所述方法包括在通过在膜上沉积包含硅，碳和任选的氧和/或氮的薄层来从膜去除光致抗蚀剂之后处理图案化的低介电常数膜。 薄层为图案化的低介电常数膜提供了富含碳的疏水性表面。 薄层还保护低介电常数膜免于随后的湿法清洗工艺和前体渗透，随后沉积在低介电常数膜上。

公开(公告)号：US07780865B2

公开(公告)日：2010-08-24

申请号：US11693005

申请日：2007-03-29

申请人： Mihaela Balseanu ,  Li-Qun Xia ,  Mei-Yee Shek ,  Hichem M'Saad

发明人： Mihaela Balseanu ,  Li-Qun Xia ,  Mei-Yee Shek ,  Hichem M'Saad

IPC分类号： C03C15/00

CPC分类号： H01L21/76834 ,  H01L21/02123 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/3185

摘要： Methods of controlling the step coverage and pattern loading of a layer on a substrate are provided. The dielectric layer may be a silicon nitride, silicon oxide, or silicon oxynitride layer. The method comprises depositing a dielectric layer on a substrate having at least one formed feature across a surface of the substrate and etching the dielectric layer with a plasma from oxygen or a halogen-containing gas to provide a desired profile of the dielectric layer on the at least one formed feature. The deposition of the dielectric layer and the etching of the dielectric layer may be repeated for multiple cycles to provide the desired profile of the dielectric layer.

摘要翻译： 提供了控制衬底上的层的阶梯覆盖和图案加载的方法。 电介质层可以是氮化硅，氧化硅或氮氧化硅层。 该方法包括在衬底上沉积介电层，该衬底具有穿过衬底的表面的至少一个形成的特征，并用等离子体从氧气或含卤素气体蚀刻介电层，以在该位置上提供介电层的理想轮廓 至少一个形成的特征。 介电层的沉积和电介质层的蚀刻可以重复多个周期以提供所需的电介质层的轮廓。

公开(公告)号：US20070287301A1

公开(公告)日：2007-12-13

申请号：US11694856

申请日：2007-03-30

申请人： Huiwen Xu ,  Mei-Yee Shek ,  Li-Qun Xia ,  Amir Al-Bayati ,  Derek Witty ,  Hichem M'Saad

发明人： Huiwen Xu ,  Mei-Yee Shek ,  Li-Qun Xia ,  Amir Al-Bayati ,  Derek Witty ,  Hichem M'Saad

IPC分类号： H01L21/312

CPC分类号： C23C16/308 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3122 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834

摘要： Methods of processing films on substrates are provided. In one aspect, the methods comprise treating a patterned low dielectric constant film after a photoresist is removed form the film by depositing a thin layer comprising silicon, carbon, and optionally oxygen and/or nitrogen on the film. The thin layer provides a carbon-rich, hydrophobic surface for the patterned low dielectric constant film. The thin layer also protects the low dielectric constant film from subsequent wet cleaning processes and penetration by precursors for layers that are subsequently deposited on the low dielectric constant film.

摘要翻译： 提供了在基板上处理膜的方法。 在一个方面，所述方法包括在通过在膜上沉积包含硅，碳和任选的氧和/或氮的薄层，在从膜去除光致抗蚀剂之后处理图案化的低介电常数膜。 薄层为图案化的低介电常数膜提供了富含碳的疏水性表面。 薄层还保护低介电常数膜免于随后的湿法清洗工艺和前体渗透，随后沉积在低介电常数膜上。

公开(公告)号：US20070232071A1

公开(公告)日：2007-10-04

申请号：US11693005

申请日：2007-03-29

申请人： Mihaela Balseanu ,  Li-Qun Xia ,  Mei-Yee Shek ,  Hichem M'Saad

发明人： Mihaela Balseanu ,  Li-Qun Xia ,  Mei-Yee Shek ,  Hichem M'Saad

IPC分类号： H01L21/465

CPC分类号： H01L21/76834 ,  H01L21/02123 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/3185

摘要： Methods of controlling the step coverage and pattern loading of a layer on a substrate are provided. The dielectric layer may be a silicon nitride, silicon oxide, or silicon oxynitride layer. The method comprises depositing a dielectric layer on a substrate having at least one formed feature across a surface of the substrate and etching the dielectric layer with a plasma from oxygen or a halogen-containing gas to provide a desired profile of the dielectric layer on the at least one formed feature. The deposition of the dielectric layer and the etching of the dielectric layer may be repeated for multiple cycles to provide the desired profile of the dielectric layer.

摘要翻译： 提供了控制衬底上的层的阶梯覆盖和图案加载的方法。 电介质层可以是氮化硅，氧化硅或氮氧化硅层。 该方法包括在衬底上沉积介电层，该衬底具有穿过衬底的表面的至少一个形成的特征，并用等离子体从氧气或含卤素气体蚀刻介电层，以在该位置上提供介电层的理想轮廓 至少一个形成的特征。 介电层的沉积和电介质层的蚀刻可以重复多个周期以提供所需的电介质层的轮廓。

公开(公告)号：US07132353B1

公开(公告)日：2006-11-07

申请号：US11195398

申请日：2005-08-02

申请人： Li-Qun Xia ,  Mei-Yee Shek ,  Troy Kim ,  Vladamir Zubkov ,  Ritwik Bhatia

发明人： Li-Qun Xia ,  Mei-Yee Shek ,  Troy Kim ,  Vladamir Zubkov ,  Ritwik Bhatia

IPC分类号： H01L21/3205

CPC分类号： H01L29/6656 ,  H01L21/3145 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a sidewall spacer on a gate electrode is described. The method includes generating a first plasma from a silicon containing precursor and oxide precursor, and forming a silicon oxy-nitride layer on the sidewall of the gate electrode. The method also includes generating a second plasma from the silicon containing precursor and a nitrogen precursor, and forming a nitride layer on the silicon oxy-nitride layer. The silicon containing precursor can flow continuously between the generation of the first and the second plasmas. Also, a method of forming a sidewall spacer on the side of a gate electrode on a substrate. The method includes forming an oxy-nitride layer on the sidewall, and forming a nitride layer on the oxy-nitride layer, where the substrate wafer is not exposed to air between the formation of the layers.

摘要翻译： 描述了在栅极上形成侧壁间隔物的方法。 该方法包括从含硅前体和氧化物前体产生第一等离子体，并在栅电极的侧壁上形成氮氧化硅层。 该方法还包括从含硅前体和氮前体产生第二等离子体，并在氮氧化硅层上形成氮化物层。 含硅前体可以在第一和第二等离子体的产生之间连续流动。 另外，在基板上的栅电极侧形成侧墙的方法。 该方法包括在侧壁上形成氮氧化物层，并且在氧化氮化物层上形成氮化物层，其中衬底晶片在层的形成之间不暴露于空气。

公开(公告)号：US07091137B2

公开(公告)日：2006-08-15

申请号：US10888110

申请日：2004-07-09

申请人： Albert Lee ,  Annamalai Lakshmanan ,  Bok Hoen Kim ,  Li-Qun Xia ,  Mei-Yee Shek Le

发明人： Albert Lee ,  Annamalai Lakshmanan ,  Bok Hoen Kim ,  Li-Qun Xia ,  Mei-Yee Shek Le

IPC分类号： H01L21/31

CPC分类号： C23C16/30 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834

摘要： Methods and apparatus are provided for processing a substrate with a bilayer barrier layer. In one aspect, the invention provides a method for processing a substrate including depositing a nitrogen containing barrier layer on a substrate surface and then depositing a nitrogen free barrier layer thereon. The barrier layer may be deposited over dielectric materials, conductive materials, or both. The bilayer barrier layer may also be used as an etch stop, an anti-reflective coating, or a passivation layer.

摘要翻译： 提供了用于处理具有双层阻挡层的衬底的方法和装置。 一方面，本发明提供了一种处理衬底的方法，包括在衬底表面上沉积含氮阻挡层，然后在其上沉积无氮阻挡层。 阻挡层可以沉积在电介质材料，导电材料或两者上。 双层阻挡层也可以用作蚀刻停止层，抗反射涂层或钝化层。