公开(公告)号：US09830272B2

公开(公告)日：2017-11-28

申请号：US13994639

申请日：2011-12-28

申请人： Iris Sorani ,  Larisa Novakovsky ,  Joseph Nuzman

发明人： Iris Sorani ,  Larisa Novakovsky ,  Joseph Nuzman

IPC分类号： G06F13/00 ,  G06F12/0891 ,  G11C7/10 ,  G06F1/32 ,  G06F12/0895

CPC分类号： G06F12/0891 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0895 ,  G11C7/1072 ,  Y02D10/14 ,  Y02D50/20

摘要： An apparatus is described. The apparatus includes a cache memory having two or more memory blocks and a central processing unit (CPU), coupled to the cache memory, to open a first memory block within the cache memory upon exiting from a low power state.

公开(公告)号：US09823731B2

公开(公告)日：2017-11-21

申请号：US14724943

申请日：2015-05-29

申请人： Intel Corporation

发明人： Nathaniel G. Burke ,  Sanjeev N. Trika

IPC分类号： G06F12/00 ,  G06F1/32 ,  G06F12/02 ,  G06F3/06 ,  G11C7/10 ,  G06F12/06

CPC分类号： G06F1/3287 ,  G06F1/32 ,  G06F1/3212 ,  G06F1/3225 ,  G06F1/3268 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/0634 ,  G06F3/0688 ,  G06F12/02 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0638 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C7/1072 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154

摘要： An apparatus includes a storage resource to store data. The data can be accessible by a host computer system. The apparatus includes a set of dynamically powered volatile memory devices that are configured to store mapping information. The mapping information maps logical addresses of received access requests to corresponding physical addresses of the storage resource to which the access requests pertain. In accordance with received mode setting information, the controller logic adaptively controls power settings of the volatile memory devices storing the mapping information. If an abundance of power such as 120 VAC power is available, more of volatile memory devices can be powered to store a greater portion of the mapping information. If only battery power is available, fewer than all of the volatile memory devices can be powered to store a smaller portion of the mapping information.

公开(公告)号：US20170329385A1

公开(公告)日：2017-11-16

申请号：US15666643

申请日：2017-08-02

申请人： QUALCOMM Incorporated

发明人： Hee Jun Park ,  Richard Gerard Hofmann ,  Yong Ju Lee

IPC分类号： G06F1/32 ,  G06F13/16

CPC分类号： G06F1/3225 ,  G06F1/3287 ,  G06F13/1668 ,  Y02D10/171

摘要： A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices. Additionally, a current/power consumption may be obtained for each memory bank within each of the plurality of volatile memory devices. Data is then copied from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower current/power consumption than the first set of memory banks. The first set of volatile memory devices and/or first set of memory banks are then placed into a power-down state.

公开(公告)号：US20170323417A1

公开(公告)日：2017-11-09

申请号：US15528915

申请日：2014-12-22

申请人： Intel Corporation

发明人： Tomasz Madajczak

IPC分类号： G06T1/20 ,  G06T15/00 ,  G06F9/30 ,  G06F13/20 ,  G06T17/10 ,  G06T15/80

CPC分类号： G06T1/20 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/30134 ,  G06F13/20 ,  G06T15/005 ,  G06T15/80 ,  G06T17/10 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

摘要： Systems and methods may provide for receiving a Reverse Polish Notation (RPN) program stream including a set of operands and a set of operations and populating a first register stack with one or more operands in the set of operands. Additionally, one or more registers in the register stack may be powered off based on a stack depth of the register stack. In one example, one or more arguments are read from the register stack and an execution is conducted of one or more operations on the arguments.

公开(公告)号：US09773532B2

公开(公告)日：2017-09-26

申请号：US14895193

申请日：2014-08-01

申请人： CANON KABUSHIKI KAISHA

发明人： Minoru Kambegawa

IPC分类号： G11C7/04 ,  G11C11/406 ,  G06F11/07 ,  G06F12/06 ,  G11C7/10

CPC分类号： G11C7/1075 ,  G06F1/206 ,  G06F1/3225 ,  G06F1/3275 ,  G06F11/0733 ,  G06F12/06 ,  G11C7/04 ,  G11C7/1072 ,  G11C11/406 ,  G11C11/40626 ,  Y02D10/14 ,  Y02D10/16

摘要： An information processing apparatus, equipped with a WideIO memory device stacked on an SOC die including a CPU, and a method of controlling the same, are provide. The apparatus obtains temperature information of each of a plurality of memories of the WideIO memory device, and generates temperature distribution information of the WideIO memory device in accordance with respective execution of a plurality of function modules. Then, the apparatus determines a refresh rate of the WideIO memory device based on the maximum temperature of the WideIO memory device, decides a period, at which the refresh rate is determined, based on an operation mode of the information processing apparatus and a change rate of the maximum temperature for a predetermined time interval, and refreshes the WideIO memory device in accordance with the determined refresh rate.

公开(公告)号：US09760474B2

公开(公告)日：2017-09-12

申请号：US14666594

申请日：2015-03-24

申请人： CenturyLink Intellectual Property LLC

发明人： Vishak Shanmugam Pillai ,  Darshan Sonbarse ,  Viswanath Seetharam ,  Manoj U P

IPC分类号： G06F9/45 ,  G06F9/44 ,  G06F11/36 ,  G06F11/34 ,  G06F1/32 ,  G06F11/07 ,  G06F11/30 ,  G06F11/32

CPC分类号： G06F11/3668 ,  G06F1/3206 ,  G06F1/3225 ,  G06F8/71 ,  G06F11/079 ,  G06F11/3003 ,  G06F11/302 ,  G06F11/3062 ,  G06F11/323 ,  G06F11/3409 ,  G06F11/3428 ,  G06F11/3466 ,  G06F11/3688 ,  G06F11/3692 ,  G06F2201/865 ,  Y02D10/34

摘要： Novel tools and techniques are provided for implementing green software applications and/or certifying software applications with a green applications efficiency (“GAE”) rating. Implementing green software applications might include performing performance tests of a software application, measuring power consumption of one or more hardware components, in response to execution of the software application during the one or more performance tests, generating a power consumption profile for the software application based on the measure power consumption, and tuning the software application such that power consumption of the one or more hardware components matches a power load caused by execution of the software application, based at least in part on the power consumption profile for the software application. Certifying software applications might include calculating an efficiency rating based on measured or calculated hardware power consumption, calculating the GAE rating for the software application, and certifying the software application with the GAE rating.

公开(公告)号：US20170255248A1

公开(公告)日：2017-09-07

申请号：US15447866

申请日：2017-03-02

申请人： ARM Limited

发明人： Ashley John CRAWFORD ,  Andrew Christopher ROSE ,  Tessil THOMAS ,  David GUILLEN FANDOS

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/13 ,  Y02D10/14

摘要： A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.

公开(公告)号：US09753524B1

公开(公告)日：2017-09-05

申请号：US15274548

申请日：2016-09-23

申请人： Juniper Networks, Inc.

发明人： Vaishali Kulkarni ,  Jeffrey G. Libby ,  Mihir Wagh

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F1/08 ,  G06F9/48

CPC分类号： G06F1/08 ,  G06F1/04 ,  G06F1/26 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0634 ,  G06F9/4881 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/171

摘要： A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to multiple processing modules, each having a first clock configuration and a second clock configuration. The dispatch module, at a first time, changes a first processing module included in the multiple processing modules from a first clock configuration to a second clock configuration. The dispatch module prohibits, at a second time within a predetermined time period and after the first time, a second processing module included in the multiple processing modules from changing from the first clock configuration to the second clock configuration if an indicator associated with a number of changes of the multiple processing modules between a first clock configuration and a second clock configuration within the predetermined time period and prior to the second time satisfies a criterion.

公开(公告)号：US09753521B2

公开(公告)日：2017-09-05

申请号：US14951150

申请日：2015-11-24

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC分类号： G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/12 ,  G06F3/06 ,  G06F9/38 ,  G06F12/0855 ,  G06F13/36

CPC分类号： G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

摘要： In an integrated circuit device that outputs data values during respective transmit intervals defined by transitions of a transmit clock, the phase of the transmit clock is shifted by half a transmit interval to enable a timing calibration operation. Thereafter, a sequence of data values is transmitted to another integrated circuit device in response to the phase-shifted transmit clock and a samples of the sequence of data values are received from the other integrated circuit device. The received samples are compared with the sequence of data values to determine a phase update value, including comparing at least one received sample with two adjacent data values within the sequence of data values, and the phase of the transmit clock is incrementally advanced or retarded according to the phase update value.

公开(公告)号：US09733692B2

公开(公告)日：2017-08-15

申请号：US15364330

申请日：2016-11-30

申请人： International Business Machines Corporation

发明人： Malcolm S. Allen-Ware ,  Shawn P. Authement ,  John C. Elliott ,  Charles R. Lefurgy ,  J. Carlos A. Pratt ,  Karthick Rajamani ,  David B. Whitworth

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F3/06

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3221 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3268 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0679 ,  G06F3/0688 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154

摘要： A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.