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431 条记录 (耗时 0.032 秒)

    Variable size FIFO memory
    33.
    发明申请
    Variable size FIFO memory 有权

    公开(公告)号：US20060072598A1

    公开(公告)日：2006-04-06

    申请号：US11237481

    申请日：2005-09-27

    申请人： Chris Haywood

    发明人： Chris Haywood

    IPC分类号： H04L12/56

    CPC分类号： G06F12/0875 ,  G06F5/10 ,  G06F2205/108 ,  H04L49/90 ,  H04L49/9042 ,  H04L49/9073

    摘要： A variable size first in first out (FIFO) memory is disclosed. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.

    Cell-based queue management in software
    34.
    发明申请
    Cell-based queue management in software 审中-公开
    基于单元的队列管理软件

    公开(公告)号：US20060067347A1

    公开(公告)日：2006-03-30

    申请号：US10953159

    申请日：2004-09-29

    申请人： Uday Naik ,  Alok Kumar

    发明人： Uday Naik ,  Alok Kumar

    IPC分类号： G06F3/00 ,  H04L12/28

    CPC分类号： H04L47/6255 ,  H04L47/50 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9073

    摘要： A system and method to implement cell-based queue management in software. Packets are received from a packet-based medium. In response, packet pointers are enqueued into a virtual output queue (“VOQ”). When a dequeue request to dequeue a cell for the VOQ is received, one of the packet pointers is speculatively prefetched from the VOQ. A cell is then transmitted onto a cell-based fabric containing at least a portion of one of the packets received from the medium and designated by a current packet pointer from among the packet pointers of the VOQ.

    摘要翻译： 一种在软件中实现基于单元的队列管理的系统和方法。 从基于分组的媒体接收分组。 作为响应，分组指针被排入虚拟输出队列（“VOQ”）。 当接收到用于VOQ的单元出队的出队请求时，从VOQ推测性地预取分组指针之一。 然后，将单元传输到基于单元的结构，其中包含从介质接收的一个分组的至少一部分，并由VOQ的分组指针中的当前分组指针指定。

    Integrated circuit and method for establishing transactions
    35.
    发明申请
    Integrated circuit and method for establishing transactions 有权
    用于建立交易的集成电路和方法

    公开(公告)号：US20060041889A1

    公开(公告)日：2006-02-23

    申请号：US10530267

    申请日：2003-10-07

    申请人： Andrei Radulescu ,  Kees Goossens

    发明人： Andrei Radulescu ,  Kees Goossens

    IPC分类号： G06F9/46

    CPC分类号： H04L47/10 ,  H04L47/32 ,  H04L49/9073

    摘要： An integrated circuit comprising a plurality of processing modules (M; I; S; T) and a network (N; RN) arranged for providing at least one connection between a first and at least one second module is provided. Said connections comprises a set of communication channels each having a set of connection properties. Said connection supports transactions comprising outgoing messages from the first module to the second module and return messages from the second module to the first module. The connection properties of the different communication channels of said connection can be adjusted independently. Therefore, the utilization of the resources of a network on chip is more efficient, since the connection between modules can be efficiently adapted to their actual requirement, such that the connection is not over dimensioned and unused network resources can be assigned to other connections.

    摘要翻译： 提供一种包括多个处理模块（M; I; S; T）和布置成用于在第一和至少一个第二模块之间提供至少一个连接的网络（N; RN）的集成电路。 所述连接包括一组通信信道，每个通信信道具有一组连接属性。 所述连接支持包括从第一模块到第二模块的输出消息的事务，并将消息从第二模块返回到第一模块。 所述连接的不同通信信道的连接属性可以独立调整。 因此，片上网络资源的利用效率更高，因为模块之间的连接可以有效地适应其实际需求，使得连接不会过大，并且未使用的网络资源可以分配给其他连接。

    Integrated circuit and method for exchanging data
    36.
    发明申请
    Integrated circuit and method for exchanging data 有权
    用于交换数据的集成电路和方法

    公开(公告)号：US20060041888A1

    公开(公告)日：2006-02-23

    申请号：US10530266

    申请日：2003-07-04

    申请人： Andrei Radulescu ,  Kees Goossens

    发明人： Andrei Radulescu ,  Kees Goossens

    IPC分类号： G06F9/46

    CPC分类号： H04L47/10 ,  H04L47/32 ,  H04L49/9073

    摘要： An integrated circuit comprising a plurality of processing modules M, S and a network N; RN arranged for providing at least one connection between a first and at least one second module M, S is provided. Said connection supports transactions comprising outgoing messages from the first module to the second modules and return messages from the second modules to the first module. Said integrated circuit comprises at least one dropping means DM for dropping data exchanged by said first and second module M, S. Accordingly, an alternative scheme for transaction completion is provided, where full and immediate transaction completion is merely applied for certain cases. The invention is based on the idea to allow the dropping of data in certain cases.

    摘要翻译： 一种集成电路，包括多个处理模块M，S和网络N; RN被设置用于在第一和至少一个第二模块M，S之间提供至少一个连接。 所述连接支持包括从第一模块到第二模块的输出消息的事务，并且将消息从第二模块返回到第一模块。 所述集成电路包括用于丢弃由所述第一和第二模块M，S交换的数据的至少一个丢弃装置DM。因此，提供了用于交易完成的备选方案，其中仅在某些情况下仅应用完全和即时交易完成。 本发明基于在某些情况下允许丢弃数据的想法。

    Method and structure for enqueuing data packets for processing
    37.
    发明申请
    Method and structure for enqueuing data packets for processing 失效
    排队处理数据包的方法和结构

    公开(公告)号：US20060039376A1

    公开(公告)日：2006-02-23

    申请号：US10868725

    申请日：2004-06-15

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    IPC分类号： H04L12/56 ,  H04L12/28

    CPC分类号： H04L49/90 ,  H04L49/9042 ,  H04L49/9073 ,  H04L69/22

    摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.

    摘要翻译： 提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。 网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。 芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。 该方法包括利用报头信息来识别分组的其余部分的位置和范围。 当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时 有空间。

    System having interfaces and switch that separates coherent and packet traffic
    39.
    发明申请
    System having interfaces and switch that separates coherent and packet traffic 审中-公开
    具有分离相干和分组业务的接口和交换机的系统

    公开(公告)号：US20050226234A1

    公开(公告)日：2005-10-13

    申请号：US11146449

    申请日：2005-06-07

    申请人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

    发明人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

    IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/28 ,  G06F13/36 ,  G06F15/167 ,  H04L12/56 ,  H04Q11/00

    CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

    摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

    摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。