公开(公告)号：US20230307037A1

公开(公告)日：2023-09-28

申请号：US17703199

申请日：2022-03-24

申请人： Kioxia Corporation

发明人： Nimrod Bregman ,  Ofir Kanter

IPC分类号： G11C11/4099 ,  G11C11/4096 ,  G11C11/54 ,  G06K9/62

CPC分类号： G11C11/4099 ,  G11C11/4096 ,  G11C11/54 ,  G06K9/6215 ,  G06K9/6256

摘要： A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain reference voltages from one or more read samples, and a plurality of sets of reference voltages. The circuit may be configured to obtain a plurality of distances, each being a distance between a point corresponding to the obtained reference voltages and a point corresponding to a respective set of reference voltages. The circuit may be configured to determine a first set of reference voltages such that a distance between the point corresponding to the obtained reference voltages and a point corresponding to the first set of reference voltage is a minimum distance of the plurality of distances. The circuit may be configured to perform read operations on locations of the flash memory with the first set of reference voltages.

公开(公告)号：US11769046B2

公开(公告)日：2023-09-26

申请号：US16353504

申请日：2019-03-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Guy M. Cohen

IPC分类号： G06N3/08 ,  G11C13/00 ,  G11C11/54 ,  H10N70/00

CPC分类号： G06N3/08 ,  G11C11/54 ,  G11C13/003 ,  G11C13/0004 ,  H10N70/8828 ,  G11C2213/79

摘要： Variable resistance devices and neural network processing systems include a first phase change memory device that has a first material that increases resistance when a set pulse is applied. A second phase change memory device has a second material that decreases resistance when a set pulse is applied.

公开(公告)号：US11756610B2

公开(公告)日：2023-09-12

申请号：US17974852

申请日：2022-10-27

申请人： Samsung Electronics Co., Ltd.

发明人： Yongmin Ju ,  Sangjoon Kim ,  Hyungwoo Lee ,  Seungchul Jung

IPC分类号： G11C7/12 ,  G11C11/54 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C7/10 ,  G11C27/02

CPC分类号： G11C11/54 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C7/1006 ,  G11C27/02

摘要： An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.

公开(公告)号：US20230267995A1

公开(公告)日：2023-08-24

申请号：US18161303

申请日：2023-01-30

申请人： Samsung Electronics Co., Ltd.

发明人： Taehwan MOON ,  Dukhyun Choe ,  Jinseong Heo ,  Hyunjae Lee

IPC分类号： G11C11/54 ,  H01L29/78 ,  H01L29/51 ,  H10B53/30 ,  H01L29/66 ,  H01L27/105 ,  H01L21/02 ,  G11C11/22

CPC分类号： G11C11/54 ,  H01L29/78391 ,  H01L29/516 ,  H10B53/30 ,  H01L29/6684 ,  H01L27/105 ,  H01L21/02175 ,  G11C11/2255 ,  G11C11/2257

摘要： Provided are a ferroelectric field effect transistor, a neural network apparatus, and an electronic apparatus. The ferroelectric field effect transistor includes: a substrate; a source protruding from an upper surface of the substrate in a first direction; a drain protruding from the upper surface of the substrate in the first direction; a channel spaced apart from the upper surface of the substrate and extending between the source and the drain in a second direction different from the first direction; a ferroelectric film surrounding an outer circumferential surface of the channel; and a gate electrode surrounding the ferroelectric film, wherein the channel has curved cross-sections having a plurality of different radii of curvature.

公开(公告)号：US20230267320A1

公开(公告)日：2023-08-24

申请号：US18168681

申请日：2023-02-14

申请人： Samsung Electronics Co., Ltd.

发明人： Taehwan MOON ,  Jinseong Heo ,  Seunggeol Nam ,  Hagyoul Bae ,  Hyunjae Lee

IPC分类号： G06N3/063 ,  H10B51/30 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/775 ,  G11C11/22 ,  G11C11/54

CPC分类号： G06N3/063 ,  H10B51/30 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/775 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/54

摘要： A ferroelectric field effect transistor includes: a source; a drain; a first channel connected to and between the source and the drain; a second channel connected to and between the source and the drain and spaced apart from the first channel; a ferroelectric layer covering the first channel and the second channel; a first gate layer disposed on the ferroelectric layer in correspondence with the first channel; a second gate layer disposed on the ferroelectric layer in correspondence with the second channel; and a gate wiring electrically connecting the first gate layer to the second gate layer, wherein the first gate layer includes a first metallic material having a first work function, and the second gate layer includes a second metallic material having a second work function, wherein the second work function is different from the first work function.

公开(公告)号：US20230244903A1

公开(公告)日：2023-08-03

申请号：US17721254

申请日：2022-04-14

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC分类号： G06N3/04 ,  G11C11/54

CPC分类号： G06N3/04 ,  G11C11/54

摘要： Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array. In certain examples, an analog array and a digital array are coupled to shared bit lines. In other examples, an analog array and a digital array are coupled to separate bit lines.

公开(公告)号：US20230229887A1

公开(公告)日：2023-07-20

申请号：US18123918

申请日：2023-03-20

申请人： Silicon Storage Technology, Inc. ,  The Regents of the University of California

发明人： Farnood Merrikh BAYAT ,  Xinjie GUO ,  Dmitri STRUKOV ,  Nhan DO ,  Hieu Van TRAN ,  Vipin TIWARI ,  Mark REITEN

IPC分类号： G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC分类号： G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/3436 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688

摘要： Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.

公开(公告)号：US20230197137A1

公开(公告)日：2023-06-22

申请号：US17558099

申请日：2021-12-21

申请人： Micron Technology, Inc.

发明人： Ezra E. Hartz ,  Joseph A. De La Cerda ,  Nicolas Soberanes ,  Christopher Moore ,  Bruce J. Ford ,  Benjamin Rivera

IPC分类号： G11C11/406 ,  G11C11/4096 ,  G11C11/54

CPC分类号： G11C11/40622 ,  G11C11/40615 ,  G11C11/4096 ,  G11C11/54 ,  G11C2211/4062

摘要： A method includes determining a quantity of refresh operations performed on a block of a memory device of a memory sub-system and determining a quantity of write operations and a quantity of read operations performed to the block. The method also includes determining the block is read dominant using the quantity of write operations and the quantity of read operations and determining whether the quantity of refresh operations has met a criteria. The method further includes, responsive to determining that the block is read dominant and that the quantity of refresh operations has met the criteria, modifying trim settings used to operate the block of the memory device.

公开(公告)号：US20230153592A1

公开(公告)日：2023-05-18

申请号：US18053182

申请日：2022-11-07

申请人： Samsung Electronics Co., Ltd.

发明人： Seunggeol NAM ,  Hagyoul Bae ,  Jinseong Heo

IPC分类号： G06N3/063 ,  H10B51/30 ,  H10B51/20 ,  G11C11/54 ,  G11C11/22

CPC分类号： G06N3/063 ,  H01L27/1159 ,  H01L27/11597 ,  G11C11/54 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257

摘要： A ferroelectric memory device may include a source, a drain, a channel layer between the source and the drain and connected to the source and the drain, a first gate electrode and a second gate electrode located on the channel layer to be spaced apart from each other, and a ferroelectric layer between the channel layer and the first gate electrode and between the channel layer and the second gate electrode. Different voltages may be applied to the first gate electrode and the second gate electrode.

公开(公告)号：US11625588B2

公开(公告)日：2023-04-11

申请号：US16809522

申请日：2020-03-04

申请人： Industrial Technology Research Institute

发明人： Tuo-Hung Hou ,  Shyh-Shyuan Sheu ,  Jeng-Hua Wei ,  Heng-Yuan Lee ,  Ming-Hung Wu

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G11C11/54 ,  G11C11/16 ,  G11C13/00

摘要： A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.