公开(公告)号：US20170025285A1

公开(公告)日：2017-01-26

申请号：US14805527

申请日：2015-07-22

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Jin Cho ,  MiaoMiao Wang ,  Hui Zang

IPC: H01L21/321 ,  H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/513 ,  H01L21/28026 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.

公开(公告)号：US20170005014A1

公开(公告)日：2017-01-05

申请号：US14789476

申请日：2015-07-01

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

IPC: H01L21/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L22/32 ,  H01L21/76895 ,  H01L21/823431 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7851

Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

Abstract translation: 实施例涉及一种方法。实施例涉及鳍式场效应晶体管（FinFET）的测试结构。 测试结构包括电耦合到FinFET的伪栅极的第一导电层和电耦合到FinFET的衬底的第二导电层。 测试结构还包括电耦合到FinFET的伪栅极的第三导电层，以及至少部分地由第一导电层和第二导电层限制的FinFET的第一区域。 所述测试结构还包括至少部分地由所述第二导电层和所述第三导电层限制的所述FinFET的第二区域，其中所述第一区域包括具有第一尺寸的第一电介质，并且其中所述第二区域包括具有 第二维度大于第一维度。

公开(公告)号：US09460996B1

公开(公告)日：2016-10-04

申请号：US14818351

申请日：2015-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/5223 ,  H01L27/013 ,  H01L28/10 ,  H01L28/60

Abstract: Integrated devices and fabrication methods thereof are presented. The methods include, for instance fabricating an integrated device comprising an inductive portion and a capacitive portion, the integrated device being at least partially embedded within an electrode. The fabricating includes providing a conductive coil at least partially within an insulator layer above a substrate, the conductive coil comprising exposed portions, wherein the inductive portion of the integrated device comprises the conductive coil; covering exposed portions of the conductive coil with a dielectric material; and forming the electrode at least partially around the dielectric covered portions of the conductive coil, the electrode being physically separated from the conductive coil by the dielectric material, wherein the capacitive portion of the integrated device comprises the electrode, the dielectric material, and the conductive coil. In one embodiment, the method further includes: exposing at least one further portion of the conductive coil; and providing another electrode in electrical contact with the at least one exposed further portion of the conductive coil.

Abstract translation: 提出了集成器件及其制造方法。 所述方法包括例如制造包括电感部分和电容部分的集成器件，所述集成器件至少部分地嵌入在电极内。 该制造包括至少部分地在衬底上方的绝缘体层内提供导电线圈，该导电线圈包括暴露部分，其中集成器件的感应部分包括导电线圈; 用介电材料覆盖导电线圈的暴露部分; 以及至少部分地围绕所述导电线圈的电介质覆盖部分形成所述电极，所述电极通过所述电介质材料与所述导电线圈物理分离，其中所述集成器件的所述电容部分包括所述电极，所述电介质材料和所述导电 线圈 在一个实施例中，该方法还包括：暴露导电线圈的至少一个另外的部分; 以及提供与导电线圈的至少一个暴露的另外部分电接触的另一电极。

公开(公告)号：US09443944B2

公开(公告)日：2016-09-13

申请号：US14541754

申请日：2014-11-14

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hui Zang ,  Balasubramanian Pranatharthiharan

IPC: H01L29/417 ,  H01L29/40 ,  H01L21/28

CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76801 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/401 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are provided. One method includes, for instance: obtaining a wafer with at least one source, drain, and gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; and forming at least one first and second small contact over the first and second contact regions. One intermediate semiconductor device includes, for instance: a wafer with a gate, source region, and drain region; at least one first contact region positioned over a portion of the source; at least one second contact region positioned over a portion of the drain; at least one first small contact positioned above the first contact region; and at least one second small contact positioned above the second contact region.

Abstract translation: 提供了用于形成具有自对准接触工艺流程和制造中线路电容减小的半导体器件的器件和方法。 一种方法包括例如：获得具有至少一个源极，漏极和栅极的晶片; 在所述至少一个源极上形成第一接触区域，以及在所述至少一个漏极上形成第二接触区域; 以及在所述第一和第二接触区域上形成至少一个第一和第二小接触。 一个中间半导体器件包括例如：具有栅极，源极区和漏极区的晶片; 位于所述源的一部分上方的至少一个第一接触区域; 至少一个第二接触区域位于所述排水管的一部分上方; 位于所述第一接触区域上方的至少一个第一小接触件; 以及位于第二接触区域上方的至少一个第二小接触件。

公开(公告)号：US09425129B1

公开(公告)日：2016-08-23

申请号：US14789160

申请日：2015-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu ,  Dingyou Zhang

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165

Abstract: Methods and structures for fabricating conductive vias in circuit structures are provided. Methods may include, for example, providing a substrate that includes a dopant and at least one trench formed in the substrate; providing an undoped semiconductor layer over a surface of the substrate within the trench; and providing a conductive material on top of dielectric layer in the trench, the conductive material forming the conductive via. The undoped semiconductor layer, having no dopant, reduces a parasitic capacitance between the conductive via and the substrate. The undoped semiconductor layer may also prevent migration of dopant from the substrate into the undoped semiconductor layer, further reducing capacitance in the circuit structure.

Abstract translation: 提供了在电路结构中制造导电通孔的方法和结构。 方法可以包括例如提供包括掺杂剂的衬底和在衬底中形成的至少一个沟槽; 在所述沟槽内的所述衬底的表面上提供未掺杂的半导体层; 并且在沟槽中的电介质层的顶部提供导电材料，导电材料形成导电通孔。 没有掺杂剂的未掺杂的半导体层降低了导电通孔和衬底之间的寄生电容。 未掺杂的半导体层还可以防止掺杂剂从衬底迁移到未掺杂的半导体层中，进一步降低电路结构中的电容。

公开(公告)号：US09401362B2

公开(公告)日：2016-07-26

申请号：US14245656

申请日：2014-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088

CPC classification number: H01L27/0922 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, a second field effect transistor formed in the substrate structure, and a third field effect transistor formed in the substrate structure. The first field effect transistor can include a first gate stack configuration, and a first threshold voltage. The second field effect transistor can include a second gate stack configuration, and a second threshold voltage. The third field effect transistor can include a third gate stack configuration, and a third threshold voltage.

Abstract translation: 在一个方面，这里阐述了具有形成在衬底结构中的第一场效应晶体管，形成在衬底结构中的第二场效应晶体管和形成在衬底结构中的第三场效应晶体管的半导体器件。 第一场效应晶体管可以包括第一栅极堆叠配置和第一阈值电压。 第二场效应晶体管可以包括第二栅极堆叠配置和第二阈值电压。 第三场效应晶体管可以包括第三栅极堆叠配置和第三阈值电压。

公开(公告)号：US09356047B2

公开(公告)日：2016-05-31

申请号：US14461700

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L21/00 ,  H01L27/12 ,  H01L23/528 ,  H01L21/84 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/845 ,  H01L23/528 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with self aligned contacts for improved process windows are provided. One method includes, for instance: obtaining a wafer with at least two gates, forming partial spacers adjacent to the at least two gates, and forming at least one contact on the wafer. One intermediate semiconductor device includes, for instance: a wafer with an isolation region, at least two gates disposed on the isolation region, at least one source region disposed on the isolation region, at least one drain region disposed on the isolation region, and at least one contact positioned between the at least two gates, wherein a first portion of the at least one contact engages the at least one source region or the at least one drain region and a second portion of the at least one contact extends above a top surface of the at least two gates.

Abstract translation: 提供了用于形成具有用于改进的工艺窗口的自对准触点的半导体器件的装置和方法。 一种方法包括：例如：获得具有至少两个栅极的晶片，形成与所述至少两个栅极相邻的部分间隔件，以及在所述晶片上形成至少一个触点。 一个中间半导体器件包括例如：具有隔离区域的晶片，设置在隔离区域上的至少两个栅极，设置在隔离区域上的至少一个源极区域，设置在隔离区域上的至少一个漏极区域，以及设置在隔离区域上的至少一个漏极区域 位于所述至少两个门之间的至少一个触点，其中所述至少一个触点的第一部分接合所述至少一个源极区域或所述至少一个漏极区域，并且所述至少一个触点的第二部分在顶表面 的至少两个门。

公开(公告)号：US09355921B2

公开(公告)日：2016-05-31

申请号：US14607160

申请日：2015-01-28

Applicant: GlobalFoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

IPC: H01L23/58 ,  H01L29/10 ,  H01L21/66 ,  H01L21/8234 ,  G03F7/20

CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

Abstract translation: 提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。 该方法包括在MPLP的第一步骤期间形成具有第一和第二栅极区的测试宏的有源区，以及在MPLP的第二步骤期间在有源区中形成第一和第二源/漏区。 该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点和确定 如果通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路，在MPLP的步骤的第一步骤和第二步骤之间发生覆盖移位。

公开(公告)号：US09293333B2

公开(公告)日：2016-03-22

申请号：US13944403

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hoon Kim

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795

Abstract: An improved method and structure for fabrication of replacement metal gate (RMG) field effect transistors is disclosed. P-type field effect transistor (PFET) gate cavities are protected while N work function metals are deposited in N-type field effect transistor (NFET) gate cavities.

Abstract translation: 公开了用于制造替代金属栅极（RMG）场效应晶体管的改进的方法和结构。 P型场效应晶体管（PFET）栅极腔被保护，而N型功能金属沉积在N型场效应晶体管（NFET）栅极腔中。

公开(公告)号：US09171922B1

公开(公告)日：2015-10-27

申请号：US14329263

申请日：2014-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L27/01 ,  H01L21/338 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L27/0688 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: One illustrative device disclosed herein includes, among other things, an active layer positioned above a layer of insulating material, a fin positioned above the active layer, a gate insulation layer positioned on the active layer and on the fin, a conductive gate structure that is positioned around at least a portion of the fin and above at least a portion of the active layer, wherein the conductive gate structure comprises at least one work function adjusting metal layer positioned on the gate insulation layer, a first channel region defined in the fin under the conductive gate structure, and a second channel region defined in the active layer under the conductive gate structure.

Abstract translation: 本文公开的一个说明性装置尤其包括位于绝缘材料层之上的有源层，位于有源层上方的鳍，位于有源层上和鳍上的栅绝缘层，导电栅结构， 定位在所述鳍片的至少一部分上方和所述有源层的至少一部分之上，其中所述导电栅极结构包括位于所述栅极绝缘层上的至少一个功函数调整金属层，限定在所述鳍下的第一沟道区域 所述导电栅极结构以及在所述有源层中限定在所述导电栅极结构之下的第二沟道区。