公开(公告)号：US20120322203A1

公开(公告)日：2012-12-20

申请号：US13593620

申请日：2012-08-24

Applicant: Zvi Or-Bach ,  Ze'ev Wurman

Inventor： Zvi Or-Bach ,  Ze'ev Wurman

IPC: H01L21/50

CPC classification number: H01L23/544 ,  H01L21/76816 ,  H01L21/76898 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/1305 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method to construct first and second configurable systems including: providing a first configurable system including a first die and a second die, where the first die is diced from a first wafer and the second die is diced from a second wafer and the first die is connected to the second die using at least one through-silicon-via (TSV); providing a second configurable system including a third die and a fourth die, where the third die is diced from a third wafer and the fourth die is diced from a fourth wafer and the third die is connected to the fourth die using at least one through-silicon-via (TSV); where processing the first wafer and the third wafer utilizes a majority of masks that are substantially same; and where the first die is larger than the third die.

Abstract translation: 一种构建第一和第二可配置系统的方法，包括：提供包括第一管芯和第二管芯的第一可配置系统，其中第一管芯从第一晶片切割，第二管芯从第二晶片切割，第一管芯为 使用至少一个穿硅通孔（TSV）连接到第二管芯; 提供包括第三管芯和第四管芯的第二可配置系统，其中第三管芯从第三晶片切割，并且第四管芯从第四晶片切割，并且第三管芯使用至少一个通孔连接到第四管芯， 硅通孔（TSV）; 其中处理第一晶片和第三晶片利用大体相同的掩模; 并且其中第一管芯大于第三管芯。

公开(公告)号：US08298875B1

公开(公告)日：2012-10-30

申请号：US13041404

申请日：2011-03-06

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Paul Lim

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Paul Lim

IPC: H01L21/20

CPC classification number: H01L27/249 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/845 ,  H01L27/0203 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/0823 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/2436 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/66621 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2224/16225 ,  H01L2224/73253

Abstract: A method to fabricate a junction-less transistor comprising: forming at least two regions of semiconductor doping; first region with a relatively high level of dopant concentration and second region with at least 1/10 lower dopant concentration, and etching away a portion of said first region for the formation of the transistor gate.

Abstract translation: 一种制造无结型晶体管的方法，包括：形成半导体掺杂的至少两个区域; 具有相对高的掺杂剂浓度水平的第一区域和具有至少1/10较低掺杂剂浓度的第二区域，以及蚀刻掉所述第一区域的一部分以形成晶体管栅极。

公开(公告)号：US08294159B2

公开(公告)日：2012-10-23

申请号：US13073268

申请日：2011-03-28

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L29/04

CPC classification number: H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H03K19/177 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

Abstract translation: 一种用于制造利用层转移的三维半导体器件的方法以及用于在预制半导体器件的顶部形成晶体管的步骤，所述预制半导体器件包括形成在晶体化半导体基底层上的晶体管和用于晶体管互连和绝缘层的金属层。 这种方法的优点是减少用于互连各种晶体管的所有金属长度。

公开(公告)号：US08273610B2

公开(公告)日：2012-09-25

申请号：US13273712

申请日：2011-10-14

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

IPC: H01L21/335 ,  H01L21/8238 ,  H01L21/30

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/16225 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Abstract translation: 一种制造半导体器件的方法，所述方法包括：提供包括半导体区域的第一单晶层，将第一单晶层与隔离层重叠，转移包含半导体区域的第二单晶层覆盖隔离层，其中第一单晶层 并且第二单晶层由基本上不同的晶体材料形成; 随后蚀刻第二单晶层作为在第二单晶层中形成至少一个晶体管的一部分。

公开(公告)号：US20120088355A1

公开(公告)日：2012-04-12

申请号：US13246157

申请日：2011-09-27

Applicant: Deepak C. Sekar ,  Zvi Or-Bach

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L21/20

CPC classification number: H01L27/2481 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2029/7857 ,  H01L2221/6835

Abstract: A method of manufacturing a semiconductor wafer, the method comprising: a first monocrystalline layer comprising semiconductor regions, overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer comprising semiconductor regions overlying the isolation layer; and etching portions of the first monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer.

Abstract translation: 一种制造半导体晶片的方法，所述方法包括：包含半导体区域的第一单晶层，将所述第一单晶层与隔离层重叠; 制备包含覆盖隔离层的半导体区域的第二单晶层; 以及蚀刻所述第一单晶层的部分，作为在所述第一单晶层上形成至少一个晶体管的一部分。

公开(公告)号：US20120086067A1

公开(公告)日：2012-04-12

申请号：US13173999

申请日：2011-06-30

Applicant: Deepak C. Sekar ,  Zvi Or-Bach

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L29/788

CPC classification number: H01L27/2481 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2029/7857 ,  H01L2221/6835

Abstract: A device, comprising: a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline, wherein said first layer comprises first transistors, wherein said second layer comprises second transistors, wherein at least one of said second transistors substantially overlays one of said first transistors, and wherein both said first transistors and said second transistors are processed following the same lithography step.

Abstract translation: 一种器件，包括：第一层和第二层，其中所述第一层和所述第二层都是单晶的，其中所述第一层包括第一晶体管，其中所述第二层包括第二晶体管，其中所述第二晶体管中的至少一个 基本上覆盖所述第一晶体管中的一个，并且其中所述第一晶体管和所述第二晶体管都在相同的光刻步骤之后被处理。

公开(公告)号：US08148728B2

公开(公告)日：2012-04-03

申请号：US13073188

申请日：2011-03-28

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L29/10

CPC classification number: H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H03K19/177 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

公开(公告)号：US08026521B1

公开(公告)日：2011-09-27

申请号：US12901890

申请日：2010-10-11

Applicant: Zvi Or-Bach ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L29/10

CPC classification number: H01L27/2481 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2029/7857 ,  H01L2221/6835

Abstract: A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Abstract translation: 一种包括半导体存储器的器件，所述器件包括：第一层和第二层转移单结晶硅，其中所述第一层包括第一多个水平取向晶体管; 其中所述第二层包括第二多个水平取向晶体管; 并且其中所述第二多个水平取向晶体管覆盖所述第一多个水平取向晶体管。

公开(公告)号：US20250133749A1

公开(公告)日：2025-04-24

申请号：US18973101

申请日：2024-12-08

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H10B63/00 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H10B10/00 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H10B61/00 ,  H10D30/62 ,  H10D30/67 ,  H10D30/69 ,  H10D84/03 ,  H10D84/80 ,  H10D86/00 ,  H10D86/01 ,  H10D88/00 ,  H10N70/00 ,  H10N70/20

Abstract: A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the first level includes control of power delivery to the at least one third transistor.

公开(公告)号：US20250126794A1

公开(公告)日：2025-04-17

申请号：US18991631

申请日：2024-12-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B53/20 ,  H10D30/63 ,  H10D30/69 ,  H10D62/834 ,  H10D64/64 ,  H10D89/10

Abstract: A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.