公开(公告)号：US20190043806A1

公开(公告)日：2019-02-07

申请号：US16157108

申请日：2018-10-11

申请人： Powertech Technology Inc.

发明人： Hung-Hsin Hsu ,  Nan-Chun Lin

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/04 ,  H01L25/00

摘要： A method of manufacturing a chip package structure comprising: disposing a first semiconductor component on a first carrier, wherein the first semiconductor component comprising a first active surface and a plurality of first pads disposed on the first active surface; forming a plurality of first conductive pillars on the first pads, wherein each of the first conductive pillars is a solid cylinder comprising a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface; forming a first encapsulant to encapsulate the first semiconductor component and the first conductive pillars, wherein the first encapsulant exposes the top surface of each of the first conductive pillars; forming a first redistribution layer on the first encapsulant, wherein the first redistribution layer is electrically connected to the first conductive pillars; and removing the first carrier.

公开(公告)号：US10177058B1

公开(公告)日：2019-01-08

申请号：US15880557

申请日：2018-01-26

申请人： Powertech Technology Inc.

发明人： Ming-Yi Wang ,  Kun-Yung Huang

IPC分类号： H01L23/52 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065

摘要： An encapsulating composition and a semiconductor package are provided. The encapsulating composition adapted to encapsulate a semiconductor die includes a photosensitive dielectric material and a polarizable compound suspended in the photosensitive dielectric material. The polarizable compound within a predetermined region of the encapsulating composition affected by an external stimulus is arranged uniformly in a thickness direction to provide a conductive path penetrating through the photosensitive dielectric material along the thickness direction. The semiconductor package includes the encapsulating composition encapsulating the semiconductor die, a first and a second redistribution layer. The first and the second redistribution layer disposed on the opposite sides of the encapsulating composition are electrically connected each other through the encapsulating composition. A manufacturing method of the semiconductor package is also provided.

公开(公告)号：US20190006305A1

公开(公告)日：2019-01-03

申请号：US15636657

申请日：2017-06-29

申请人： Powertech Technology Inc.

发明人： Kun-Yung Huang

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L21/768

摘要： A manufacturing method of a semiconductor package structure is provided. The method includes the following steps. A first redistribution layer is formed on a first surface of a semiconductor substrate. A plurality of through holes and an opening are formed on the semiconductor substrate. A chip is disposed in the opening of the semiconductor substrate. A conductive through via is formed in the through holes to electrically connect the first redistribution layer. A second redistribution layer is formed on a second surface of the semiconductor substrate opposite to the first surface to electrically connect the chip. The second redistribution layer is electrically connected to the first redistribution layer by the conductive through via. A plurality of conductive structures are formed on the second redistribution layer. A semiconductor package structure is also provided.

公开(公告)号：US20180366344A1

公开(公告)日：2018-12-20

申请号：US15626165

申请日：2017-06-18

申请人： Powertech Technology Inc.

发明人： Kun-Yung Huang ,  Chih-Fu Lung ,  Shih-Chi Li ,  Mei-Chen Lee ,  Chung-Hao Tsai ,  Chi-Liang Wang

IPC分类号： H01L21/48

摘要： A manufacturing method of a redistribution layer is provided. The method includes the following steps. A patterned sacrificial layer is formed on a carrier. An actuate angle is formed between a side wall of the patterned sacrificial layer and the carrier. A first conductive layer is formed. The first conductive layer includes a plurality of first portions formed on the carrier and a plurality of second portions formed on the patterned sacrificial layer. The patterned sacrificial layer and the second portions of the first conductive layer are removed from the carrier. Another manufacturing method of a redistribution layer is also provided.

公开(公告)号：US10128211B2

公开(公告)日：2018-11-13

申请号：US15630940

申请日：2017-06-22

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chang ,  Yong-Cheng Chuang ,  Yu-Tso Lin

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L23/16 ,  H01L21/56

摘要： A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

公开(公告)号：US20180226442A1

公开(公告)日：2018-08-09

申请号：US15427055

申请日：2017-02-08

申请人： Powertech Technology Inc.

发明人： Kun-Yung Huang

IPC分类号： H01L27/146

CPC分类号： H01L27/14618 ,  H01L27/14636 ,  H01L27/14683

摘要： An image sensor including a device chip, a plurality of spacers, a dam layer, a lid, and a plurality of conductive terminals. The device chip has a first surface and a second surface opposite to the first surface. The device chip includes a sensing area on the first surface and a plurality of conductive pads surrounding the sensing area. The spacers are over the first surface of the device chip. The dam layer encapsulates the conductive pads and the spacers. The lid is over the dam layer. The conductive terminals are over the second surface of the device chip and are electrically connected to the conductive pads. In addition, a manufacturing method of the image sensor is also provided.

公开(公告)号：US20180211936A1

公开(公告)日：2018-07-26

申请号：US15630940

申请日：2017-06-22

申请人： Powertech Technology Inc.

发明人： Chia-Wei Chang ,  Yong-Cheng Chuang ,  Yu-Tso Lin

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/544

CPC分类号： H01L24/96 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/544 ,  H01L24/19 ,  H01L24/20 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511

摘要： A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer and an alignment structure are disposed over the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the alignment structure are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and exposes the polished cross-sectional surfaces and the alignment structure. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires and the alignment structure.

公开(公告)号：US09972554B2

公开(公告)日：2018-05-15

申请号：US15432932

申请日：2017-02-15

申请人： POWERTECH TECHNOLOGY INC.

发明人： Li-Chih Fang ,  Chia-Chang Chang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang ,  Kee-Wei Chung ,  Chia-Wen Lien

IPC分类号： H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L27/146

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/15311

摘要： A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.

公开(公告)号：US20180076179A1

公开(公告)日：2018-03-15

申请号：US15640595

申请日：2017-07-03

申请人： Powertech Technology Inc.

发明人： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5226 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L25/03 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/214 ,  H01L2924/00

摘要： A stacked-type chip package structure includes a first chip, first terminals, a first redistribution layer, a first encapsulant, a second chip, second terminals, a second redistribution layer and through pillars. Each first chip includes a first active surface and first pads located on the first active surface. The first terminals are disposed on the first pads. The first redistribution layer is electrically connected to the first chip. The first encapsulant encapsulates the first chip and exposes top surfaces of the first terminals. The second chip is disposed over the first encapsulant. The second chip includes a second active surface and second pads located on the second active surface. The second terminals are disposed on the second pads. The second redistribution layer is electrically connected to the second chip. The through pillars electrically connect the first redistribution layer and the second redistribution layer.

公开(公告)号：US20180076158A1

公开(公告)日：2018-03-15

申请号：US15600804

申请日：2017-05-22

申请人： Powertech Technology Inc.

发明人： Li-Chih Fang ,  Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

CPC分类号： H01L24/09 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/37001

摘要： A chip package structure includes a chip, an encapsulant, a dielectric layer and a patterned circuit layer. The chip includes an active surface and a plurality of pads disposed on the active surface. The encapsulant encapsulates the chip and exposes active surface, wherein the encapsulant includes a concave surface and a back surface opposite to the concave surface, the concave surface exposes the active surface and is dented toward the back surface. The dielectric layer covers the concave surface and the active surface and includes a plurality of openings exposing the pads, wherein the opening includes a slanted side surface and the angle between the slanted side surface and the active surface is an acute angle. The patterned circuit layer is disposed on the dielectric layer and electrically connected to the pads through the openings.