公开(公告)号：US20080211552A1

公开(公告)日：2008-09-04

申请号：US11712349

申请日：2007-03-01

Applicant: Chao-Cheng Lu

Inventor： Chao-Cheng Lu

IPC: H03L7/00 ,  H02M7/217

CPC classification number: H02M3/33592 ,  Y02B70/1475

Abstract: The present controllable synchronous rectifier employs a Lus semiconductor to set synchronous rectification action in quadrant 1 of output characteristics of the conventional power MOSFETs. By controlling the voltage level of the gate-source voltage, the drain current can be controlled in the synchronous rectifier. Further, in combination with a protect opposite circuit to transfer a sinusoidal wave power supply or pulse power supply to a direct current power output, the synchronous rectifier is an indispensable high efficiency rectifier in the industry.

Abstract translation: 本可控同步整流器采用Lus半导体在常规功率MOSFET的输出特性的象限1中设置同步整流动作。 通过控制栅源电压的电压电平，可以在同步整流器中控制漏极电流。 此外，同步整流器与保护相反的电路结合，将正弦波电源或脉冲电源传送到直流电源输出，同步整流器是业界不可或缺的高效率整流器。

公开(公告)号：US20080197461A1

公开(公告)日：2008-08-21

申请号：US11706193

申请日：2007-02-15

Applicant: Chen-Hua Yu ,  Hui-Lin Chang ,  Yung-Cheng Lu ,  Mirng-Ji Lii ,  Yung-Ching Chen

Inventor： Chen-Hua Yu ,  Hui-Lin Chang ,  Yung-Cheng Lu ,  Mirng-Ji Lii ,  Yung-Ching Chen

IPC: H01L21/60 ,  B23K37/00 ,  H01L23/495

CPC classification number: H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/45012 ,  H01L2224/45013 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4516 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49175 ,  H01L2224/78268 ,  H01L2224/78301 ,  H01L2224/85043 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/20751 ,  H01L2924/00 ,  H01L2924/01006 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An apparatus for wire bonding and a capillary tool thereof are provided. An exemplary embodiment of a capillary tool capable of a wire bonding comprises a body having a first internal channel of a first diameter for accommodating a flow of a conductive wire. A compressible head is connected to the body, having a second internal channel of a second diameter for accommodating the flow of the conductive wire, wherein the first diameter is fixed and the second diameter is variable, the second diameter is not more than the first diameter and a diameter the conductive wire flowed through the compressible head is adjustable. An integrated circuit (IC) package is also provided.

Abstract translation: 提供一种用于引线接合的装置及其毛细管工具。 能够引线接合的毛细管工具的示例性实施例包括具有用于容纳导线流动的第一直径的第一内部通道的主体。 可压缩头连接到主体，具有用于容纳导线流动的第二直径的第二内部通道，其中第一直径是固定的，第二直径是可变的，第二直径不大于第一直径 并且流过可压缩头的导线的直径是可调节的。 还提供集成电路（IC）封装。

公开(公告)号：US07412888B2

公开(公告)日：2008-08-19

申请号：US11591617

申请日：2006-11-02

Applicant: Chia-Yi Chu ,  Heng-Chung Chang ,  Chuan-Wei Wang ,  Chih-Ming Sun ,  Wei-Leun Fang ,  Shiang-Cheng Lu ,  Hsieh-Shen Hsieh ,  Horng-Jou Wang ,  Tai-Kang Shing ,  Huang-Kun Chen

Inventor： Chia-Yi Chu ,  Heng-Chung Chang ,  Chuan-Wei Wang ,  Chih-Ming Sun ,  Wei-Leun Fang ,  Shiang-Cheng Lu ,  Hsieh-Shen Hsieh ,  Horng-Jou Wang ,  Tai-Kang Shing ,  Huang-Kun Chen

IPC: G01P15/125

CPC classification number: G01P15/125 ,  G01P2015/0814

Abstract: An accelerometer includes a fixing unit and a movable unit. The fixing unit has a plurality of first electrode parts and a plurality of second electrode parts. The movable unit is connected with the fixing unit and includes a body having an opening, a plurality of third electrode parts and a plurality of fourth electrode parts. The third electrode parts are disposed at an outer side of the body with respect to the first electrode parts, respectively. The fourth electrode parts are disposed at the inner side of the body in the opening, and are disposed respectively with respect to the second electrode parts, respectively.

Abstract translation: 加速度计包括固定单元和可移动单元。 固定单元具有多个第一电极部分和多个第二电极部分。 可移动单元与固定单元连接，并且包括具有开口的主体，多个第三电极部分和多个第四电极部分。 第三电极部分分别相对于第一电极部分设置在主体的外侧。 第四电极部分设置在开口内的主体的内侧，分别相对于第二电极部分设置。

公开(公告)号：US07405481B2

公开(公告)日：2008-07-29

申请号：US11004065

申请日：2004-12-03

Applicant: Keng-Chu Lin ,  Yung-Cheng Lu ,  Shwang-Ming Cheng

Inventor： Keng-Chu Lin ,  Yung-Cheng Lu ,  Shwang-Ming Cheng

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an integrated circuit chip, a conductive line is formed in a first IMD layer. The conductive line is formed of a conductive line material that tends to form an oxide when exposed to an oxygen-containing substance. A glue layer is formed on the conductive line. The glue layer is formed of a non-oxygen-containing material capable of providing an oxygen barrier over the conductive line. The glue layer has a hardness greater than that of the conductive line. The glue layer preferably has a thickness between about 15 angstroms and about 75 angstroms. The etch stop layer is formed on the glue layer. The etch stop layer has a hardness greater than that of the glue layer. A second IMD layer is formed on the etch stop layer. The etch stop layer and/or the second IMD layer may be formed with a material comprising oxygen without oxidizing the conductive line.

Abstract translation: 在集成电路芯片中，在第一IMD层中形成导线。 导电线由暴露于含氧物质时易于形成氧化物的导电线材料形成。 在导电线上形成胶层。 胶层由能够在导电线上提供氧阻隔的非含氧材料形成。 胶层的硬度大于导电线的硬度。 胶层优选地具有在约15埃至约75埃之间的厚度。 蚀刻停止层形成在胶层上。 蚀刻停止层的硬度大于胶层的硬度。 在蚀刻停止层上形成第二IMD层。 蚀刻停止层和/或第二IMD层可以由包含氧的材料形成而不氧化导电线。

公开(公告)号：US20080085607A1

公开(公告)日：2008-04-10

申请号：US11523674

申请日：2006-09-19

Applicant: Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

Inventor： Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

IPC: H01L21/31

CPC classification number: H01L21/3105 ,  H01L21/823807 ,  H01L29/7843

Abstract: A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.

Abstract translation: 一种形成半导体结构的方法包括提供包括第一器件区域的衬底，在第一器件区域中形成金属氧化物半导体（MOS）器件，在MOS器件上形成应力层，并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线（UV）固化，激光固化，电子束固化及其组合组成的组。

公开(公告)号：US20080080251A1

公开(公告)日：2008-04-03

申请号：US11905211

申请日：2007-09-28

Applicant: Yao-Wen Chang ,  Tao-Cheng Lu

Inventor： Yao-Wen Chang ,  Tao-Cheng Lu

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/0475 ,  G11C16/28

Abstract: A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value.

Abstract translation: 读取双位存储单元的方法包括控制终端，第一终端和第二终端。 双位存储单元分别具有第一位存储节点和靠近第一终端和第二终端的第二位存储节点。 首先，分别对控制端子和第一端子施加控制电压和读取电压。 第二端子接地以测量第一端子的第一输出电流值。 然后，控制电压和读取电压分别施加到控制端子和第二端子。 第一端子接地以测量第二端子的第二输出电流值。 之后，根据第一输出电流值和第二输出电流值同时读取第一位存储节点的位状态和第二位存储节点的位状态。

公开(公告)号：US20080032472A1

公开(公告)日：2008-02-07

申请号：US11524000

申请日：2006-09-20

Applicant: Chen-Hua Yu ,  Ming-Shih Yeh ,  Chih-Hsien Lin ,  Yung-Cheng Lu ,  Hui-Lin Chang

Inventor： Chen-Hua Yu ,  Ming-Shih Yeh ,  Chih-Hsien Lin ,  Yung-Cheng Lu ,  Hui-Lin Chang

IPC: H01L21/8242

CPC classification number: H01L21/76849 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/76826

Abstract: A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.

Abstract translation: 形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成金属化层，其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸 进入低k电介质层，对低k电介质层进行处理以形成亲水性顶表面，以及在溶液中的金属特征上镀覆盖层。

公开(公告)号：US20080013640A1

公开(公告)日：2008-01-17

申请号：US11700359

申请日：2007-01-31

Applicant: Cheng Lu ,  Richard Locarni ,  Richard Hummel ,  Frank Haunstein ,  Michael Dombrowski

Inventor： Cheng Lu ,  Richard Locarni ,  Richard Hummel ,  Frank Haunstein ,  Michael Dombrowski

IPC: H04L23/02

CPC classification number: H04L5/14 ,  H04L5/023 ,  H04L5/1438 ,  H04L27/2601

Abstract: A multi-dimensional Burst Link Access Streaming Transmission (BLAST) architecture, which provides flexible physical apparatus for balanced performance of data throughput, latency, and reliability of transmission (e.g. graceful degradation). A schedule is sent from a master node to alert targeted nodes regarding messages to be sent. The master node uses a P-Band transmission link operating a regular intervals to synchronize the system in preparation for receipt of a message over a synchronous link. Each node has the capability of sending and receiving synchronous and asynchronous messages.

Abstract translation: 多维突发链路接入流传输（BLAST）架构，其提供用于平衡数据吞吐量，延迟和传输可靠性（例如，优雅降级）的灵活物理设备。 从主节点发送计划以针对要发送的消息向目标节点警报。 主节点使用以规则间隔操作的P波段传输链路来同步系统以准备通过同步链路接收消息。 每个节点具有发送和接收同步和异步消息的能力。

公开(公告)号：US07291870B2

公开(公告)日：2007-11-06

申请号：US10904475

申请日：2004-11-12

Applicant: Chun-Hsiang Lai ,  Shin Su ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

Inventor： Chun-Hsiang Lai ,  Shin Su ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC: H01L29/72

CPC classification number: H01L27/0266 ,  H01L29/7436 ,  H01L29/87

Abstract: An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.

Abstract translation: 耦合到输入焊盘的静电放电（ESD）保护电路包括形成在衬底中并耦合到输入焊盘的二极管; 在衬底中形成的P阱; 在P深井中形成N井; N阱中的第一P +掺杂区; 以及形成在所述衬底上的NMOS晶体管，包括栅极，源极和漏极，其中所述漏极形成在所述N阱中并耦合到Vcc，并且所述源极形成在所述P阱中; 以及形成在P深井中的第二P +掺杂区域。 ESD保护电路使用比常规ESD保护电路更小的面积。

公开(公告)号：US07253524B2

公开(公告)日：2007-08-07

申请号：US10797224

申请日：2004-03-10

Applicant: Zhen-Cheng Wu ,  Tzu-Jen Chou ,  Weng Chang ,  Yung-Cheng Lu ,  Syun-Ming Jang ,  Mong-Song Liang

Inventor： Zhen-Cheng Wu ,  Tzu-Jen Chou ,  Weng Chang ,  Yung-Cheng Lu ,  Syun-Ming Jang ,  Mong-Song Liang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76835 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor substrate has a first copper layer, on which an etch stop layer and a dielectric layer are successively formed. A second copper layer penetrates the dielectric layer and the etch stop layer to electrically connect to the first metal layer. The etch stop layer has a dielectric constant smaller than 3.5, and the dielectric layer has a dielectric constant smaller than 3.0.

Abstract translation: 半导体衬底具有第一铜层，其上依次形成有蚀刻停止层和电介质层。 第二铜层穿透电介质层和蚀刻停止层以电连接到第一金属层。 蚀刻停止层的介电常数小于3.5，电介质层的介电常数小于3.0。