公开(公告)号：US20140038088A1

公开(公告)日：2014-02-06

申请号：US13564334

申请日：2012-08-01

Applicant: Hsin-Chang Lee ,  Yun-Yue Lin ,  Pei-Cheng Hsu ,  Chia-Jen Chen ,  Ta-Cheng Lien ,  Anthony Yen

Inventor： Hsin-Chang Lee ,  Yun-Yue Lin ,  Pei-Cheng Hsu ,  Chia-Jen Chen ,  Ta-Cheng Lien ,  Anthony Yen

IPC: G03F1/24

CPC classification number: G03F1/22 ,  G03F1/80

Abstract: A method of fabricating an extreme ultraviolet (EUV) mask is disclosed. The method includes providing a substrate, forming a reflective multilayer (ML) over the substrate, forming a buffer layer over the reflective ML, forming an absorption layer over the buffer layer and forming a capping layer over the absorption layer. The capping layer and the absorption layer are etched to form the EUV mask.

Abstract translation: 公开了一种制造极紫外（EUV）掩模的方法。 该方法包括提供衬底，在衬底上形成反射多层（ML），在反射ML上形成缓冲层，在缓冲层上形成吸收层，并在吸收层上形成覆盖层。 蚀刻覆盖层和吸收层以形成EUV掩模。

公开(公告)号：US20130323625A1

公开(公告)日：2013-12-05

申请号：US13486015

申请日：2012-06-01

Applicant: Chih-Chiang Tu ,  Hsin-Chang Lee ,  Jong-Yuh Chang ,  Chia-Jen Chen ,  Chun-Lang Chen

Inventor： Chih-Chiang Tu ,  Hsin-Chang Lee ,  Jong-Yuh Chang ,  Chia-Jen Chen ,  Chun-Lang Chen

IPC: G03F1/00 ,  G03F1/26 ,  G03F1/36 ,  G03F1/50

CPC classification number: G03F1/36 ,  G03F1/50 ,  G03F1/58 ,  G03F1/80

Abstract: Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.

Abstract translation: 公开了掩模毛坯和掩模的结构，以及制造掩模的方法。 当过程经过蚀刻步骤三次时，新的掩模坯料和掩模包括三层蚀刻停止层，以防止损坏石英基板。 三重蚀刻停止层可以包括含有氮（TaN）的钽的第一子层，含有氧（TaO）的钽的第二子层和TaN的第三子层。 或者，三重蚀刻停止层可以包括SiON材料的第一子层，TaO材料的第二子层和SiON材料的第三子层。 另一个替代方案可以是一层低蚀刻速率的MoxSiyONz材料，当该工艺经过蚀刻步骤三次时，其可以防止对石英衬底的损坏。 通过使用各种光学邻近校正规则在掩模空白上定义岛掩模。

公开(公告)号：US20130280644A1

公开(公告)日：2013-10-24

申请号：US13451767

申请日：2012-04-20

Applicant: Yun-Yue Lin ,  Ta-Cheng Lien ,  Hsin-Chang Lee ,  Anthony Yen ,  Chia-Jen Chen

Inventor： Yun-Yue Lin ,  Ta-Cheng Lien ,  Hsin-Chang Lee ,  Anthony Yen ,  Chia-Jen Chen

IPC: G03F1/48 ,  G03F1/26 ,  G03F1/30 ,  G03F1/22

CPC classification number: G03F1/48 ,  G03F1/22 ,  G03F1/26 ,  G03F1/30 ,  G03F1/32 ,  G03F1/50

Abstract: A photomask includes a low thermal expansion material (LTEM) substrate, a patterned opaque layer over the LTEM substrate, and a patterned capping layer over the opaque layer. The patterned capping layer includes a transition metal material for suppressing haze growth, such as metal oxide, metal nitride, or metal oxynitride. The material in the capping layer reacts with a hydrogenic compound from a lithography environment to for an atomic level hydrogen passivation layer. The passivation layer has superior ability to suppress photo-induced haze defect growth on the photomask surface, to improve production cycle time and reduce the production cost.

公开(公告)号：US20130260573A1

公开(公告)日：2013-10-03

申请号：US13437075

申请日：2012-04-02

Applicant: Hsin-Chang Lee ,  Yun-Yue Lin ,  Hung-Chang Hsieh ,  Chia-Jen Chen ,  Yih-Chen Su ,  Ta-Cheng Lien ,  Anthony Yen

Inventor： Hsin-Chang Lee ,  Yun-Yue Lin ,  Hung-Chang Hsieh ,  Chia-Jen Chen ,  Yih-Chen Su ,  Ta-Cheng Lien ,  Anthony Yen

IPC: H01L21/033

CPC classification number: G03F1/76

Abstract: A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.

Abstract translation: 公开了一种制造具有应力消除处理的光刻掩模的方法。 该方法包括提供衬底并在衬底上沉积不透明层。 将不透明层图案化以形成图案化掩模。 通过使用辐射照射对图案化掩模施加应力消除处理。

公开(公告)号：US20130221443A1

公开(公告)日：2013-08-29

申请号：US13407507

申请日：2012-02-28

Applicant: Yu Chao LIN ,  Chih-Tang PENG ,  Shun-Hui YANG ,  Ryan Chia-Jen CHEN ,  Chao-Cheng CHEN

Inventor： Yu Chao LIN ,  Chih-Tang PENG ,  Shun-Hui YANG ,  Ryan Chia-Jen CHEN ,  Chao-Cheng CHEN

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L21/3065 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a plurality of first trenches having a first width and extending downward from the substrate major surface to a first height, wherein a first space between adjacent first trenches defines a first fin; and a plurality of second trenches having a second width less than first width and extending downward from the substrate major surface to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin.

Abstract translation: 本发明涉及鳍状场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括主表面的衬底; 多个第一沟槽，具有第一宽度并从所述衬底主表面向下延伸到第一高度，其中相邻第一沟槽之间的第一空间限定第一鳍片; 以及多个第二沟槽，其具有小于第一宽度的第二宽度并且从所述衬底主表面向下延伸到大于所述第一高度的第二高度，其中相邻第二沟槽之间的第二空间限定第二鳍片。

公开(公告)号：US20130219350A1

公开(公告)日：2013-08-22

申请号：US13398923

申请日：2012-02-17

Applicant: Hsin-Chang Lee ,  Chia-Jen Chen ,  Lee-Chih Yeh ,  Anthony Yen

Inventor： Hsin-Chang Lee ,  Chia-Jen Chen ,  Lee-Chih Yeh ,  Anthony Yen

IPC: G06F17/50

CPC classification number: G03F1/00 ,  G03F1/20 ,  G03F1/22 ,  G03F1/36 ,  G03F1/42 ,  G03F1/70 ,  G06F17/5081 ,  G06F19/00 ,  G21K5/00

Abstract: A method for reducing layer overlay errors by synchronizing the density of mask material in the frame area across the masks in a set is disclosed. An exemplary method includes creating a mask design database corresponding to a mask and containing a die area with one or more dies and a frame area outside the die area. Fiducial features within the frame area are identified, and from the fiducial features, an idle frame area is identified. A reference mask design, which corresponds to a reference mask configured to be aligned with the mask, is used to determine a reference density for the idle frame area. The idle frame area of the mask design database is modified to correspond to the reference density. The modified mask design database is then available for further use including manufacturing the mask.

Abstract translation: 公开了一种通过使一组中的掩模之间的框区域中的掩模材料的密度同步来减少层重叠误差的方法。 一种示例性方法包括创建对应于掩模并且包含具有一个或多个管芯的管芯区域和管芯区域外部的框架区域的掩模设计数据库。 识别帧区域内的基准特征，并从基准特征中识别空闲帧区域。 使用对应于被配置为与掩模对准的参考掩模的参考掩模设计来确定空闲帧区域的参考密度。 修改掩模设计数据库的空闲帧区域以对应于参考密度。 然后，修改的掩模设计数据库可用于进一步使用，包括制造掩模。

公开(公告)号：US20130202992A1

公开(公告)日：2013-08-08

申请号：US13369061

申请日：2012-02-08

Applicant: Chia-Jen Chen ,  Anthony Yen ,  Hsin-Chang Lee ,  Sheng-Chi Chin

Inventor： Chia-Jen Chen ,  Anthony Yen ,  Hsin-Chang Lee ,  Sheng-Chi Chin

IPC: G03F1/54 ,  G03F1/50

CPC classification number: G03F1/42 ,  G03F1/50 ,  G03F1/84

Abstract: Provided is a method for reducing phase defects on many different types of semiconductor mask blanks. The method includes receiving a semiconductor mask blank substrate, creating alignment marks on the surface of the substrate, performing an inspection of the surface of the substrate to locate a plurality of surface defects, and repairing the plurality of surface defects on the surface of the substrate. A semiconductor mask is also provided that includes a repaired substrate a multilayer stack comprising a plurality of molybdenum and silicon layers, a capping layer, an absorber layer, and in some instances a photoresist layer.

Abstract translation: 提供了一种用于减少许多不同类型的半导体掩模坯料上的相缺陷的方法。 该方法包括：接收半导体掩模空白基板，在基板的表面上产生对准标记，对基板的表面进行检查以定位多个表面缺陷，以及修复基板表面上的多个表面缺陷 。 还提供了一种半导体掩模，其包括修复的衬底，包括多个钼和硅层的多层叠层，覆盖层，吸收层，并且在一些情况下为光致抗蚀剂层。

公开(公告)号：US20130105915A1

公开(公告)日：2013-05-02

申请号：US13286605

申请日：2011-11-01

Applicant: Po-Chi WU ,  Ryan Chia-Jen CHEN

Inventor： Po-Chi WU ,  Ryan Chia-Jen CHEN

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L21/02186 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/32137 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A metal-oxide-semiconductor (MOS) device having a selectable threshold voltage determined by the composition of an etching solution contacting a metal layer. The MOS device can be either a p-type or n-type MOS and the threshold voltage is selectable for both types of MOS devices. The etching solution is either an oxygen-containing solution or a fluoride-containing solution. The threshold voltage is selected by adjusting the flow rate of inert gases into an etching chamber to control the concentration of oxygen gas or nitrogen trifluoride.

Abstract translation: 具有通过接触金属层的蚀刻溶液的组成确定的可选择阈值电压的金属氧化物半导体（MOS）器件。 MOS器件可以是p型或n型MOS，并且对于两种类型的MOS器件都可以选择阈值电压。 蚀刻溶液是含氧溶液或含氟化物溶液。 通过调节惰性气体进入蚀刻室的流量来控制阈值电压，以控制氧气或三氟化氮的浓度。

公开(公告)号：US08357617B2

公开(公告)日：2013-01-22

申请号：US12371672

申请日：2009-02-16

Applicant: Matt Yeh ,  Shun Wu Lin ,  Chi-Chun Chen ,  Ryan Chia-Jen Chen ,  Yi-Hsing Chen ,  Chien-Hao Chen ,  Donald Y. Chao ,  Kuo-Bin Huang

Inventor： Matt Yeh ,  Shun Wu Lin ,  Chi-Chun Chen ,  Ryan Chia-Jen Chen ,  Yi-Hsing Chen ,  Chien-Hao Chen ,  Donald Y. Chao ,  Kuo-Bin Huang

IPC: H01L21/302

CPC classification number: H01L21/28105 ,  H01L21/28123 ,  H01L21/28158 ,  H01L21/31111 ,  H01L21/32139 ,  H01L29/401

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

公开(公告)号：US08273632B2

公开(公告)日：2012-09-25

申请号：US13281862

申请日：2011-10-26

Applicant: Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

Inventor： Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

IPC: H01L21/336

CPC classification number: H01L21/32139 ,  H01L21/0276 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/823437 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成可图案化层。 该方法包括在可图案层上形成第一层。 该方法包括在第一层上形成第二层。 第二层比第一层薄得多。 该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。 该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。 第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。 该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。