公开(公告)号：US20120299096A1

公开(公告)日：2012-11-29

申请号：US13186660

申请日：2011-07-20

Applicant: Ker Hsiao HUO ,  Ru-Yi SU ,  Fu-Chih YANG ,  Chun Lin TSAI ,  Chih-Chang CHENG

Inventor： Ker Hsiao HUO ,  Ru-Yi SU ,  Fu-Chih YANG ,  Chun Lin TSAI ,  Chih-Chang CHENG

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/404 ,  H01L29/0607 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816

Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

Abstract translation: 横向DMOS晶体管设置有源极区，漏极区和导电栅。 漏极区域通过在导电栅极下方侵入的场氧化物与导电栅极横向分离。 横向DMOS晶体管可以形成为跑道状结构，其中导电栅极包括直线部分和弯曲部分并被源极区域包围。 布置在导电栅极和捕获的漏极之间是一层或多层次的层间电介质材料。 一组或多组隔离的导体引线形成在电介质层中或介质层上，并且可以设置在多个器件级。 隔离导电引线增加了横向DMOS晶体管的击穿电压，特别是在电场拥挤可能会降低击穿电压的弯曲区域中。

公开(公告)号：US20120126334A1

公开(公告)日：2012-05-24

申请号：US12953665

申请日：2010-11-24

Applicant: Ru-Yi Su ,  Chia-Chin Shen ,  Yu Chuan Liang ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

Inventor： Ru-Yi Su ,  Chia-Chin Shen ,  Yu Chuan Liang ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L27/0251

Abstract: The present disclosure provides a semiconductor device that includes a substrate having a resistor element region and a transistor region, a floating substrate in the resistor element region of the substrate, an epitaxial layer disposed over the floating substrate, and an active region defined in the epitaxial layer, the active region surrounded by isolation structures. The device further includes a resistor block disposed over an isolation structure, and a dielectric layer disposed over the resistor block, the isolation structures, and the active region. A method of fabricating such semiconductor devices is also provided.

Abstract translation: 本公开提供一种半导体器件，其包括具有电阻元件区域和晶体管区域的衬底，衬底的电阻器元件区域中的浮置衬底，设置在浮置衬底上的外延层以及限定在外延层中的有源区 层，被隔离结构包围的活性区域。 该器件还包括设置在隔离结构上的电阻器块，以及设置在电阻器块，隔离结构和有源区域上的电介质层。 还提供了一种制造这种半导体器件的方法。

公开(公告)号：US20110241114A1

公开(公告)日：2011-10-06

申请号：US12753486

申请日：2010-04-02

Applicant: RU-YI SU ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Chia-Chin Shen ,  Eric Huang ,  Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

Inventor： RU-YI SU ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Chia-Chin Shen ,  Eric Huang ,  Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7835 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816

Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well.

Abstract translation: 在本公开中提供了高电压金属氧化物半导体横向扩散装置（HV LDMOS）及其制造方法。 该器件包括半导体衬底，形成在衬底上的栅极结构，在栅极结构的任一侧上的衬底中形成的源极和漏极，在衬底中形成的第一掺杂阱和形成在第一衬底中的第二掺杂阱 好。 第二井的一部分围绕源，第二井的另一部分从第一井的第一部分横向延伸。

公开(公告)号：US09373619B2

公开(公告)日：2016-06-21

申请号：US13195156

申请日：2011-08-01

Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L29/02 ,  H01L27/08 ,  H01L29/40 ,  H01L29/06 ,  H01L49/02 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/0646 ,  H01L23/535 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/36 ,  H01L29/404 ,  H01L29/405 ,  H01L29/66136 ,  H01L29/7835 ,  H01L29/8611

Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor.

Abstract translation: 提供高压半导体器件。 高电压半导体器件包括其中布置有掺杂阱的衬底。 掺杂阱和衬底具有相反的掺杂极性。 高电压半导体器件包括设置在掺杂阱上的绝缘器件。 高电压半导体器件包括设置在绝缘器件上的细长电阻器。 电阻器的非远端部分耦合到掺杂阱。 高电压半导体器件包括邻近电阻器设置的高压结端接（HVJT）器件。

公开(公告)号：US09099556B2

公开(公告)日：2015-08-04

申请号：US13213409

申请日：2011-08-19

Applicant: Chen-Liang Chu ,  Fei-Yuh Chen ,  Yi-Sheng Chen ,  Shih-Kuang Hsiao ,  Chun Lin Tsai ,  Kong-Beng Thei

Inventor： Chen-Liang Chu ,  Fei-Yuh Chen ,  Yi-Sheng Chen ,  Shih-Kuang Hsiao ,  Chun Lin Tsai ,  Kong-Beng Thei

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/41775 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/78 ,  H01L29/7823 ,  H01L29/7835

Abstract: A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.

Abstract translation: 半导体器件包括具有通道区域的有源区域和与栅极介电层下方的沟道区域邻接的至少一个翼区域。 所述至少一个机翼区域可以是穿过所述通道区域的两个对称翼区域。

公开(公告)号：US08598679B2

公开(公告)日：2013-12-03

申请号：US12956025

申请日：2010-11-30

Applicant: Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

Inventor： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L23/52

CPC classification number: H01L27/0288 ,  H01L23/5256 ,  H01L27/0255 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

Abstract translation: 本公开提供了一种半导体器件，其包括晶体管，其包括衬底，源极，漏极和栅极以及堆叠在晶体管上的熔丝。 保险丝包括耦合到晶体管的漏极的阳极触点，阴极触点和分别经由第一肖特基二极管和第二肖特基二极管耦合到阴极触点和阳极触点的电阻器。 还提供了一种制造这种半导体器件的方法。

公开(公告)号：US20130256679A1

公开(公告)日：2013-10-03

申请号：US13434431

申请日：2012-03-29

Applicant: Fu-Wei YAO ,  Chen-Ju YU ,  King-Yuen WONG ,  Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Fu-Chih YANG ,  Chun Lin TSAI

Inventor： Fu-Wei YAO ,  Chen-Ju YU ,  King-Yuen WONG ,  Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/778 ,  H01L21/20

CPC classification number: H01L29/452 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/28575 ,  H01L29/0843 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

Abstract translation: 高电子迁移率晶体管（HEMT）包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 自杀剂源特征和自杀物排放特征通过第二III-V化合物层与第一III-V化合物层接触。 栅极电极设置在第一III-V化合物层的一部分之间，位于自对准硅化物源特征和自对准硅化物漏极特征之间。

公开(公告)号：US20130032862A1

公开(公告)日：2013-02-07

申请号：US13195156

申请日：2011-08-01

Applicant: Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

Inventor： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L27/06 ,  H01L21/335

CPC classification number: H01L29/0646 ,  H01L23/535 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/36 ,  H01L29/404 ,  H01L29/405 ,  H01L29/66136 ,  H01L29/7835 ,  H01L29/8611

Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor.

Abstract translation: 提供高压半导体器件。 高电压半导体器件包括其中布置有掺杂阱的衬底。 掺杂阱和衬底具有相反的掺杂极性。 高电压半导体器件包括设置在掺杂阱上的绝缘器件。 高电压半导体器件包括设置在绝缘器件上的细长电阻器。 电阻器的非远端部分耦合到掺杂阱。 高电压半导体器件包括邻近电阻器设置的高压结端接（HVJT）器件。

公开(公告)号：US08159029B2

公开(公告)日：2012-04-17

申请号：US12256009

申请日：2008-10-22

Applicant: Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

Inventor： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC: H01L29/76

CPC classification number: H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7835

Abstract: A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.

Abstract translation: 半导体器件包括半导体衬底，形成在衬底中的源极区和漏极区，形成在衬底上的栅极结构，该衬底设置在源极和漏极区之间，第一隔离结构形成在栅极结构和栅极结构之间的衬底中 漏极区域，所述第一隔离结构包括位于所述漏极区域的边缘附近的突起。 每个突起包括在沿着漏极区域的边缘的第一方向上测量的宽度和在垂直于第一方向的第二方向上测量的长度，并且相邻的突起彼此间隔一定距离。

公开(公告)号：US20110163376A1

公开(公告)日：2011-07-07

申请号：US12652294

申请日：2010-01-05

Applicant: Chih-Chang CHENG ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Chia-Chin Shen ,  Eric Huang ,  Fu Chin Yang ,  Chun Lin Tsai ,  Hsiao-Chin Tuan

Inventor： Chih-Chang CHENG ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Chia-Chin Shen ,  Eric Huang ,  Fu Chin Yang ,  Chun Lin Tsai ,  Hsiao-Chin Tuan

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L24/16 ,  H01L24/48 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.

Abstract translation: 高压（HV）器件包括设置在衬底中的第一掺杂剂类型的阱区。 第二掺杂剂类型的第一阱区域设置在第一掺杂剂类型的阱区域中。 隔离结构至少部分地设置在第一掺杂剂类型的阱区中。 第一栅电极设置在隔离结构和第二掺杂剂类型的第一阱区之上。 第二掺杂剂类型的第二阱区设置在第一掺杂剂类型的阱区中。 第二掺杂剂类型的第二阱区域与第二掺杂剂类型的第一阱区域间隔开。 第二栅电极设置在第二掺杂剂类型的第一阱区域和第二掺杂剂类型的第二阱区域之间和之上。