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    NONVOLATILE MEMORY AND FABRICATION METHOD THEREOF
    41.
    发明申请
    NONVOLATILE MEMORY AND FABRICATION METHOD THEREOF 有权
    非易失性存储器及其制造方法

    公开(公告)号：US20110059592A1

    公开(公告)日：2011-03-10

    申请号：US12943487

    申请日：2010-11-10

    Applicant: Tseung-Yuen TSENG ,  Chun-Chieh Lin ,  Chao-Cheng Lin

    Inventor： Tseung-Yuen TSENG ,  Chun-Chieh Lin ,  Chao-Cheng Lin

    IPC: H01L21/02

    CPC classification number: H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1625

    Abstract: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.

    Abstract translation: 公开了在基板上形成的非易失性存储器和制造方法。 包含金属层的底部电极设置在基板上。 包含LaNiO3膜的缓冲层设置在金属层上。 包含SrZrO 3膜的电阻层设置在缓冲层上。 顶电极设置在电阻层上。

    DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area
    46.
    发明授权
    DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area 有权
    DRAM电容器结构具有增加的电极支持，用于防止工艺损坏和暴露的电极表面，以增加电容器面积

    公开(公告)号：US07161204B2

    公开(公告)日：2007-01-09

    申请号：US11098112

    申请日：2005-04-04

    Applicant: Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Fu-Liang Yang ,  Chia-Hui Lin ,  Chanming Hu

    Inventor： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Fu-Liang Yang ,  Chia-Hui Lin ,  Chanming Hu

    IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC classification number: H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

    Abstract: A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

    Abstract translation: 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案化，以在电容器之间提供保护层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

    STRAINED-CHANNEL SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME
    48.
    发明申请
    STRAINED-CHANNEL SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
    应变通道半导体结构及其制造方法

    公开(公告)号：US20060220119A1

    公开(公告)日：2006-10-05

    申请号：US11423457

    申请日：2006-06-12

    Applicant: Chun-Chieh Lin ,  Yee-Chia Yeo

    Inventor： Chun-Chieh Lin ,  Yee-Chia Yeo

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

    CPC classification number: H01L21/823425 ,  H01L21/76224 ,  H01L21/823412 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7848

    Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

    Abstract translation: 应变通道半导体结构及其制造方法。 应变通道半导体结构包括由具有第一自然晶格常数的第一半导体材料构成的衬底。 沟道区设置在衬底中，并且栅堆叠设置在应变沟道区上方，一对源极/漏极区相对地设置在与沟道区相邻的衬底中，其中源/漏区中的每一个包括晶格 - 错配区域包括具有第二自然晶格常数而不是第一自然晶格常数的第二半导体材料，对应于栅极堆叠的内侧和外侧，并且至少一个外侧横向接触基板的第一半导体材料。

    Methods of forming semiconductor devices with high-k gate dielectric
    50.
    发明申请
    Methods of forming semiconductor devices with high-k gate dielectric 有权
    用高k栅极电介质形成半导体器件的方法

    公开(公告)号：US20060177997A1

    公开(公告)日：2006-08-10

    申请号：US11377105

    申请日：2006-03-16

    Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

    Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

    IPC: H01L21/20

    CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    Abstract: A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.

    Abstract translation: 提供一种制造集成电路的方法。 第一栅介质部分形成在第一晶体管区域中的衬底上。 第一栅介质部分包括第一高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 在第二晶体管区域中的衬底上形成第二栅介质部分。 第二栅介质部分包括第一高电容率介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度不同于第一等效氧化硅厚度。

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