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    NITRIDE SEMICONDUCTOR TRANSISTOR DEVICE
    41.
    发明申请
    NITRIDE SEMICONDUCTOR TRANSISTOR DEVICE 审中-公开

    公开(公告)号：US20200185506A1

    公开(公告)日：2020-06-11

    申请号：US16705587

    申请日：2019-12-06

    申请人： Riichiro SHIROTA ,  Shinichiro TAKATANI

    发明人： Riichiro SHIROTA ,  Shinichiro TAKATANI

    IPC分类号： H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06 ,  H01L29/778 ,  H01L29/417

    摘要： A nitride semiconductor transistor device is disclosed. The device includes a first nitride semiconductor layer disposed over a substrate, and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor disposed over the first nitride semiconductor layer. Over the second nitride semiconductor layer, a first insulating film, a charge-storing gate electrode, a second insulating film, and a second gate electrode are formed in order thereon. A source electrode and a drain electrode are disposed over the second nitride semiconductor layer interposing the charge-storing gate electrode in a plane direction. The device further includes a first gate electrode capacitively coupling with the charge-storing gate electrode with an insulating film therebetween forming a first capacitor, and the charge-storing gate electrode is charged by an electron injection from the first gate electrode through the first capacitor.

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITE-IN METHOD THEREOF
    43.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITE-IN METHOD THEREOF 有权
    非易失性半导体存储器件及其写入方法

    公开(公告)号：US20130176783A1

    公开(公告)日：2013-07-11

    申请号：US13527251

    申请日：2012-06-19

    申请人： Makoto SENOO ,  Hideki ARAKAWA ,  Riichiro SHIROTA

    发明人： Makoto SENOO ,  Hideki ARAKAWA ,  Riichiro SHIROTA

    IPC分类号： G11C16/10

    CPC分类号： G11C16/10 ,  G11C16/20

    摘要： TASK: to minimize variations of the threshold voltage distribution after programming and obtain a high-speed rewriting characteristic. MEANS FOR SOLVING THE PROBLEM: A non-volatile semiconductor memory device includes a non-volatile memory cell array and a control circuit for controlling writing-in to the memory cell array, wherein before or after an erasing process where data of written-in memory cells is erased, the control circuit detects a programming speed when writing-in to the memory cell array, determines a programming start voltage corresponding to the programming speed for every block or every word line, stores the determined programming start voltage in the memory cell array and reads-out the programming start voltage from the memory cell array to write-in predetermined data.

    摘要翻译： 任务：最小化编程后阈值电压分布的变化，并获得高速重写特性。 解决问题的手段：非易失性半导体存储器件包括非易失性存储单元阵列和用于控制对存储单元阵列的写入的控制电路，其中在写入存储器的数据的擦除处理之前或之后 单元被擦除时，控制电路在写入存储单元阵列时检测编程速度，确定与每个块或每个字线对应的编程速度的编程开始电压，将所确定的编程开始电压存储在存储单元阵列中 并从存储单元阵列读出编程开始电压以写入预定数据。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE
    45.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权
    具有元件分离区域的非挥发性半导体存储器件

    公开(公告)号：US20120168846A1

    公开(公告)日：2012-07-05

    申请号：US13421248

    申请日：2012-03-15

    申请人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    发明人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11548 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/788

    摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

    摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。

    Method for programming a memory structure
    48.
    发明授权
    Method for programming a memory structure 有权
    用于编程存储器结构的方法

    公开(公告)号：US07855918B2

    公开(公告)日：2010-12-21

    申请号：US12144645

    申请日：2008-06-24

    申请人： Riichiro Shirota ,  Ching-Hsiang Hsu ,  Cheng-Jye Liu

    发明人： Riichiro Shirota ,  Ching-Hsiang Hsu ,  Cheng-Jye Liu

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418

    摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

    摘要翻译： 存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。 每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。 一种用于对存储器结构进行编程的方法包括分别向第一存储单元和第二存储单元提供第一栅极偏置电压和第二栅极偏置电压，提高第一存储单元的沟道电压的绝对值以产生电子和空穴 通过栅极引起的漏极泄漏或带对带隧穿在第二存储单元的漏极处对，并将所产生的电子和空穴对的电子注入到第一存储单元的电荷存储装置中，以对第一存储单元 。

    Channel carrier discharging in a NAND flash memory on an insulating substrate or layer
    49.
    发明授权
    Channel carrier discharging in a NAND flash memory on an insulating substrate or layer 失效
    通道载体在绝缘基板或层上的NAND闪速存储器中放电

    公开(公告)号：US07791948B2

    公开(公告)日：2010-09-07

    申请号：US12165211

    申请日：2008-06-30

    申请人： Riichiro Shirota ,  Fumitaka Arai

    发明人： Riichiro Shirota ,  Fumitaka Arai

    IPC分类号： G11C16/02 ,  G11C16/06

    CPC分类号： G11C16/3431 ,  G11C16/0483 ,  G11C16/10

    摘要： A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, both ends of each NAND cell unit being coupled to a source line and a bit line, wherein the device has such a carrier discharging mode as to discharge channel carriers in the NAND cell unit to at least one of the source line and the bit line.

    摘要翻译： 半导体存储器件包括：设置在绝缘基板或绝缘层上的半导体层; 在半导体层中限定的有源区域，其中埋设有器件绝缘膜; 以及形成在有源区上的NAND单元单元，每个NAND单元单元包括串联连接的多个电可重写和非易失性存储单元，每个NAND单元单元的两端耦合到源极线和位线，其中， 器件具有这样的载流子放电模式，以将NAND单元单元中的沟道载流子放电到源极线和位线中的至少一个。