公开(公告)号：US5307464A

公开(公告)日：1994-04-26

申请号：US621641

申请日：1990-12-03

申请人： Yasushi Akao ,  Shiro Baba ,  Yoshiyuki Miwa ,  Terumi Sawase ,  Yuji Sato ,  Shigeki Masumura

发明人： Yasushi Akao ,  Shiro Baba ,  Yoshiyuki Miwa ,  Terumi Sawase ,  Yuji Sato ,  Shigeki Masumura

IPC分类号： G06F13/12 ,  G06F15/78 ,  G06F13/00

CPC分类号： G06F13/124 ,  G06F15/7814

摘要： A single chip microprocessor 1 includes a CPU 2 and a sub-processor 5 for software implementation of peripheral functions of the microprocessor 1. Sub-processor 5 includes electrically writable internal storage devices microprogram memory unit 13 and sequence control memory unit 62 for storing the software. Peripheral functions are defined and/or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define and/or modify the peripheral functions is the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13. Additionally, the microprogram memory unit 13 provides microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information regarding the order of selection of the multiple address registers MAR0 to MAR11. One of the address registers MAR0 to MAR11 is selected each time the sequence control memory unit 62 is read. A microaddress stored in the selected address register is then supplied to the microprogram memory unit 13.

摘要翻译： 单片微处理器1包括用于软件实现微处理器1的外围功能的CPU 2和子处理器5.子处理器5包括电可写内部存储设备微程序存储单元13和用于存储软件的顺控控制存储单元62 。 通过将软件写入存储器单元13和62来定义和/或修改外围功能。因此，定义和/或修改外围功能所花费的时间是编程存储器单元13和62所花费的时间。子 处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址的地址控制电路14.另外，微程序存储单元13向执行单元16提供微指令。顺序控制存储器 单元62是还包括多个地址寄存器MAR0至MAR11的地址控制电路14的一部分。 顺序控制存储器单元62用于存储关于多个地址寄存器MAR0至MAR11的选择顺序的信息。 每次读序列控制存储器单元62选择地址寄存器MAR0至MAR11中的一个。 存储在选择的地址寄存器中的微地址然后被提供给微程序存储单元13。

公开(公告)号：US07558944B2

公开(公告)日：2009-07-07

申请号：US12075131

申请日：2008-03-07

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F15/76 ,  G06F13/00 ,  G06F9/26

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

公开(公告)号：US20080028134A1

公开(公告)日：2008-01-31

申请号：US11860762

申请日：2007-09-25

申请人： Kiyoshi MATSUBARA ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi MATSUBARA ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G06F13/00

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 具有电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储器单元的可重写非易失性存储器，并且被设置为便于闪存擦除以及多个存储器单元的各个单元的选择性擦除。 用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号 操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

公开(公告)号：US06343357B1

公开(公告)日：2002-01-29

申请号：US09632332

申请日：2000-08-03

申请人： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

发明人： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC分类号： G06F1500

CPC分类号： G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

摘要翻译： 采用通用寄存器方法的微型计算机MCU能够具有使用效率和低系统成本的小程序容量或高程序存储器，同时具有如在具有固定长度指令的RISC机器中简化指令解码的优点 通过采用固定长度指令格式，该格式具有功率为2但比为指令执行馈送的最大数据字长的位数小的固定长度指令格式。 并且，通过注意代码位来执行编码除法的控制。

公开(公告)号：USRE36482E

公开(公告)日：2000-01-04

申请号：US729132

申请日：1996-10-11

申请人： Shiro Baba

发明人： Shiro Baba

IPC分类号： G11C11/406 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F15/78

CPC分类号： G06F12/0653

摘要： A microprocessor has a register in which attributive data corresponding to a memory to be coupled to the microprocessor is written, and a control circuit which controls address signals to be supplied to the memory in accordance with the attributive data. The attributive data is composed of range data for discriminating ranges of address data supplied to an address bus, system data indicative of addressing systems of the memories corresponding to the respective address ranges, and bit number data indicative of numbers of address bits of the memories. Thus, in a case where the memory to be accessed is of an address multiplexing system as in a dynamic RAM, the address data of the address bus is divided into row address data and column address data, which are then supplied to the memory in time division.

摘要翻译： 微处理器具有寄存器，其中写入与要耦合到微处理器的存储器对应的属性数据;以及控制电路，其根据属性数据控制提供给存储器的地址信号。 属性数据由用于区分提供给地址总线的地址数据的范围的范围数据，指示对应于各个地址范围的存储器的寻址系统的系统数据以及指示存储器的地址位数的位数数据组成。 因此，在要访问的存储器是如在动态RAM中的地址多路复用系统的情况下，地址总线的地址数据被划分为行地址数据和列地址数据，然后及时被提供给存储器 师。

公开(公告)号：US5991545A

公开(公告)日：1999-11-23

申请号：US478730

申请日：1995-06-07

申请人： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

发明人： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC分类号： G06F9/28 ,  G06F7/483 ,  G06F7/52 ,  G06F7/527 ,  G06F7/535 ,  G06F7/537 ,  G06F9/30 ,  G06F9/302 ,  G06F9/305 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/22

CPC分类号： G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

摘要： Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

摘要翻译： 这里公开了采用通用寄存器方法的微计算机MCU。 微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过 采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。 并且，通过注意码位来执行编码除法的控制。

公开(公告)号：US5884092A

公开(公告)日：1999-03-16

申请号：US725481

申请日：1996-10-04

申请人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F5/01 ,  G06F7/00 ,  G06F7/76 ,  G06F9/302 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38 ,  G06F15/78 ,  G06F17/10 ,  G06F15/00

CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/30043

摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chippthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing.The digital signal processing unit is made a calculation unit that handles fixed-point data, and an instruction calling for execution of a fixed-point data calculation is provided separately from the conventional integer calculation instruction. When, in the data transfer between the digital signal processing unit and memories or external circuits, data shorter in bit length than the calculation precision is transferred, the calculation unit has a function to input and output data to and from the higher-order side of the register in which the data is stored and the fixed point data transfer instruction is provided separately from the conventional integer data transfer instruction.This invention can eliminate additional correction processing necessitated when the integer data processing unit is made to execute the digitalsignal processing.

摘要翻译： 在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理器被安装在同一个发明中，防止了数量的增加 由计算器处理的不同类型的数据引起的处理步骤，从而提高数字信号处理的效率。 数字信号处理单元是处理定点数据的计算单元，并且与常规整数计算指令分开提供调用执行定点数据计算的指令。 当在数字信号处理单元和存储器或外部电路之间的数据传送中，位长度比传送计算精度更短的数据时，计算单元具​​有向数据信号处理单元和存储器或外部电路的高阶侧输入和输出数据的功能， 存储数据的寄存器和固定点数据传送指令与传统的整数数据传送指令分开提供。 本发明可以消除当整数数据处理单元执行数字信号处理时所需的附加校正处理。

公开(公告)号：US5867726A

公开(公告)日：1999-02-02

申请号：US630320

申请日：1996-04-10

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F12/06 ,  G06F9/30 ,  G06F9/34 ,  G06F9/355 ,  G06F9/38 ,  G06F12/00 ,  G06F13/16 ,  G06F15/76 ,  G06F15/78

CPC分类号： G06F9/3893 ,  G06F15/7817 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

公开(公告)号：US5771363A

公开(公告)日：1998-06-23

申请号：US607568

申请日：1996-02-27

申请人： Naoki Mitsuishi ,  Shiro Baba ,  Hiromi Nagayama ,  Tsutomu Hayashi ,  Yukihide Hayakawa

发明人： Naoki Mitsuishi ,  Shiro Baba ,  Hiromi Nagayama ,  Tsutomu Hayashi ,  Yukihide Hayakawa

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355 ,  G06F12/00 ,  G06F12/06 ,  G06F15/00

CPC分类号： G06F9/30014 ,  G06F12/0623 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30167 ,  G06F9/30192 ,  G06F9/321 ,  G06F9/324 ,  G06F9/342 ,  G06F9/35

摘要： Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in a CPU 1 of 8 bits so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU. The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU. This register can be used in its entirety, dividing it in half or by dividing it in quarters. As a result, the register can be excellently used on a software or hardware to reduce the logical and physical scales of the CPU. In respect of the latch of the address data using the register wholly or partially, moreover, the address space to be linearly used can be easily expanded.

摘要翻译： 扩展寄存器E0至E7被添加到内置于8位的CPU 1中的现有的通用寄存器R0至R7中，使得包括所添加的扩展寄存器的所有寄存器可以作为访问存储器的地址数据全部被掌握 或类似物。 地址操作在包括扩展寄存器和对应的通用寄存器的单元中执行。 包括扩展寄存器在内的所有寄存器被作为地址数据的一个单位来处理，以处理在地址操作中引起的进位或借位。 由于扩展寄存器的应用限于地址的生成，所以减少了可执行指令的种类或组合的数量，而不会严重降低数据处理能力，从而抑制CPU的逻辑和物理尺度的增加。 通过将16位的扩展寄存器Ei添加到8位CPU的16位的通用寄存器RiH和RiL，将寄存器整体提供32位。 该寄存器可以全部使用，将其除以一半或将其除以季度。 因此，可以在软件或硬件上极大地使用寄存器，以减少CPU的逻辑和物理尺寸。 此外，关于使用寄存器的地址数据的锁存全部或部分，可以容易地扩展要线性使用的地址空间。

公开(公告)号：US5511211A

公开(公告)日：1996-04-23

申请号：US102156

申请日：1993-08-04

申请人： Yasushi Akao ,  Shiro Baba ,  Terumi Sawase ,  Yoshimune Hagiwara

发明人： Yasushi Akao ,  Shiro Baba ,  Terumi Sawase ,  Yoshimune Hagiwara

IPC分类号： G06F9/24 ,  G06F9/445 ,  G06F15/78 ,  G06F9/312 ,  G06F13/40 ,  G06F15/20

CPC分类号： G06F8/60 ,  G06F15/7814 ,  G06F9/24

摘要： In developing the function of a data processing system using a semiconductor integrated circuit for data processing, comprising a non-volatile logical function block to which data is written electrically and a logical operation block utilizing the logical function block to execute the logic operation, data corresponding to the required specification and function of the system is written in the logical function block. Thereby, flexibility is obtained for setting and changing the required function to the semiconductor integrated circuit. The semiconductor integrated circuit also has an operation specification written to the logical block by a writing device designed to write to a non-volatile semiconductor storage device thereby improving the convenience of setting the functions required of the semiconductor integrated circuit.

摘要翻译： 在开发使用半导体集成电路进行数据处理的数据处理系统的功能中，包括电子地写入数据的非易失性逻辑功能块和利用逻辑功能块执行逻辑运算的逻辑运算块，对应的数据 将系统的所需规格和功能写入逻辑功能块。 由此，可以获得将半导体集成电路所需的功能设定和变更的灵活性。 半导体集成电路还具有通过设计成写入非易失性半导体存储装置的写入装置写入逻辑块的操作规范，从而提高了设置半导体集成电路所需功能的便利性。