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222 条记录 (耗时 0.041 秒)

    Inexpensive method of fabricating a higher performance capacitance density MIMcap integrable into a copper interconnect scheme
    42.
    发明授权
    Inexpensive method of fabricating a higher performance capacitance density MIMcap integrable into a copper interconnect scheme 失效
    制造更高性能的电容密度MIMcap的廉价方法可以集成到铜互连方案中

    公开(公告)号：US07687867B2

    公开(公告)日：2010-03-30

    申请号：US11846248

    申请日：2007-08-28

    申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  William J. Murphy ,  Vidhya Ramachandran

    发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  William J. Murphy ,  Vidhya Ramachandran

    IPC分类号： H01L29/72

    CPC分类号： H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode. The bottom and top plate electrodes can comprise the same or different conductive metal.

    摘要翻译： 提供了一种将MIM电容器集成到导电互连级别中的方法，具有低成本影响，并且提供了比现有集成方法高的产量，可靠性和性能。 这通过将用于MIM电容器电平对准的先前级别的电介质凹入，然后MIM电容器膜的沉积和图案化来实现。 具体地，该方法包括提供包括布线层的衬底，所述布线层包括形成在电介质层中的至少一个导电布线; 选择性地去除所述电介质层的一部分以使所述电介质层在所述至少一个导电互连的上表面下方凹陷; 在所述至少一个导电互连和所述凹入的介电层上形成电介质叠层; 以及在介电叠层上形成金属绝缘体金属（MIM）电容器。 MIM电容器包括底板电极，电介质和顶板电极。 底板和顶板电极可以包括相同或不同的导电金属。

    Interdigitated vertical parallel capacitor
    44.
    发明授权
    Interdigitated vertical parallel capacitor 有权
    交叉垂直并联电容器

    公开(公告)号：US08378450B2

    公开(公告)日：2013-02-19

    申请号：US12548484

    申请日：2009-08-27

    申请人： Roger A. Booth, Jr. ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He

    发明人： Roger A. Booth, Jr. ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L28/90 ,  H01L23/5223 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

    摘要翻译： 叉指结构可以包括至少一个第一金属线，平行于至少一个第一金属线并与至少一个第一金属线分离的至少一个第二金属线，以及接触至少一个第一金属线的端部的第三金属线 第一金属线并且与所述至少一个第二金属线分离。 所述至少一个第一金属线不垂直接触任何金属通孔，并且至少一个第二金属线可垂直接触至少一个金属通孔。 多层交错结构可以垂直堆叠。 替代地，叉指结构可以包括多个第一金属线和多个第二金属线，每个金属线不垂直地接触任何金属通孔。 交错结构的多个实例可以横向复制和邻接，具有或不具有旋转和/或垂直堆叠以形成电容器。

    Process for single and multiple level metal-insulator-metal integration with a single mask
    46.
    发明授权
    Process for single and multiple level metal-insulator-metal integration with a single mask 有权
    单层和多层金属绝缘体金属与单一掩模集成的工艺

    公开(公告)号：US08207568B2

    公开(公告)日：2012-06-26

    申请号：US11162661

    申请日：2005-09-19

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

    IPC分类号： H01L29/92

    CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

    摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

    摘要翻译： 制造MIM电容器和MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

    INTEGRATED BEOL THIN FILM RESISTOR
    50.
    发明申请
    INTEGRATED BEOL THIN FILM RESISTOR 有权
    集成波形薄膜电阻器

    公开(公告)号：US20090065898A1

    公开(公告)日：2009-03-12

    申请号：US12271942

    申请日：2008-11-17

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

    摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。