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111 条记录 (耗时 0.034 秒)

    Lateral superjunction extended drain MOS transistor
    41.
    发明授权
    Lateral superjunction extended drain MOS transistor 有权
    横向超结延长漏极MOS晶体管

    公开(公告)号：US08580650B2

    公开(公告)日：2013-11-12

    申请号：US13284054

    申请日：2011-10-28

    申请人： Marie Denison ,  Sameer Pendharkar

    发明人： Marie Denison ,  Sameer Pendharkar

    IPC分类号： H01L21/76

    CPC分类号： H01L29/7816 ,  H01L21/76224 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

    摘要： An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.

    摘要翻译： 一种集成电路，其包含在漂移区域中具有深半导体（SC）RESURF沟槽的扩展漏极MOS晶体管，其中每个深的SC RESURF沟槽在与漂移区接触的沟槽的侧壁处具有半导体RESURF层。 半导体RESURF层具有与漂移区相反的导电类型。 深的SC RESURF沟槽具有至少5：1的深度：宽度比，并且不延伸穿过漂移区域的底部表面。 通过蚀刻尺寸不足的沟槽和反向掺杂侧壁区以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。 通过蚀刻沟槽并在侧壁区域上生长外延层以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。

    Thick gate oxide for LDMOS and DEMOS
    42.
    发明授权
    Thick gate oxide for LDMOS and DEMOS 有权
    LDMOS和DEMOS的厚栅氧化物

    公开(公告)号：US08470675B2

    公开(公告)日：2013-06-25

    申请号：US13274698

    申请日：2011-10-17

    申请人： Seetharaman Sridhar ,  Sameer Pendharkar

    发明人： Seetharaman Sridhar ,  Sameer Pendharkar

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823456 ,  H01L21/823462

    摘要： A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor.

    摘要翻译： 一种形成集成电路的工艺，包括形成用于离子注入低电压晶体管的虚拟氧化物层，用较薄的栅极电介质层代替低电压晶体管区域中的虚拟氧化物，并将用于DEMOS的栅极电介质的虚拟氧化物 或LDMOS晶体管。 一种形成集成电路的工艺，包括形成用于离子注入低压和中压晶体管的虚拟氧化物层，用较薄的栅介质层代替低电压晶体管中的虚拟氧化物，用中间电压晶体管替代中间电压晶体管中的虚拟氧化物， 另一栅极电介质层，并且保留用于DEMOS或LDMOS晶体管的栅极电介质的虚拟氧化物。

    Lateral metal oxide semiconductor drain extension design
    43.
    发明授权
    Lateral metal oxide semiconductor drain extension design 有权
    横向金属氧化物半导体漏极扩展设计

    公开(公告)号：US08426281B2

    公开(公告)日：2013-04-23

    申请号：US12961885

    申请日：2010-12-07

    申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

    发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar

    IPC分类号： H01L21/336

    CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

    摘要： A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.

    摘要翻译： 包括源极和漏极区域105,107以及绝缘区域115和板状结构140的半导体器件100.源极和漏极区域在半导体衬底110上或半导体衬底110中。绝缘区域在半导体衬底上或半导体衬底中并且位于 源极和漏极区域。 绝缘区域具有薄层120和厚层122.厚层包括彼此分离并且跨越源极和漏极区域之间的长度135延伸的多个绝缘条132。 板结构位于源极和漏极区之间，其中板结构位于薄层上，厚层的部分，板结构具有一个或多个导电带143，其直接位于多个 绝缘条纹

    INTEGRATED LATERAL HIGH VOLTAGE MOSFET
    44.
    发明申请
    INTEGRATED LATERAL HIGH VOLTAGE MOSFET 有权
    集成式横向高压MOSFET

    公开(公告)号：US20120112277A1

    公开(公告)日：2012-05-10

    申请号：US13284011

    申请日：2011-10-28

    申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

    发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7816 ,  H01L21/265 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

    摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

    摘要翻译： 一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。 下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。 一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。 一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

    Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom
    45.
    发明授权
    Trench isolation comprising process having multiple gate dielectric thicknesses and integrated circuits therefrom 有权
    包括具有多个栅介质厚度的工艺和其集成电路的沟槽隔离

    公开(公告)号：US07888196B2

    公开(公告)日：2011-02-15

    申请号：US12345072

    申请日：2008-12-29

    申请人： Seetharaman Sridhar ,  Sameer Pendharkar ,  Dan M. Mosher

    发明人： Seetharaman Sridhar ,  Sameer Pendharkar ,  Dan M. Mosher

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823462 ,  H01L21/76229 ,  H01L21/823481 ,  H01L21/823857 ,  H01L21/823878

    摘要： A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness

    摘要翻译： 一种制造集成电路（IC）的方法，所述集成电路（IC）包括第一多个MOS晶体管，所述第一多个MOS晶体管具有在第一区域中具有第一厚度的第一栅极电介质，以及第二多个MOS晶体管， 其中所述第一厚度<所述第二厚度。 提供具有半导体表面的衬底。 具有厚度为nlE的焊盘电介质层;在包括第二区域的半导体表面上形成第二厚度，其中焊盘介电层为第二栅极电介质提供第二厚度的至少一部分。 在包括第二区域的半导体表面上形成硬掩模层。 通过蚀刻通过焊盘介电层和半导体表面的一部分形成多个沟槽隔离区域。 多个沟槽隔离区域填充有介电填充材料以形成沟槽隔离区域，然后去除硬掩模层。 在第二栅极电介质上形成图案化的栅极电极层，其中所述图案化的栅极电极层在至少一个沟槽隔离区域的表面上延伸。 然后完成第一和第二区域中的MOS晶体管的制造。

    Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof
    46.
    发明授权
    Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof 有权
    非均匀掺杂高压漏极延迟晶体管及其制造方法

    公开(公告)号：US07618870B2

    公开(公告)日：2009-11-17

    申请号：US12357653

    申请日：2009-01-22

    申请人： Shanjen Pan ,  Sameer Pendharkar ,  James R. Todd

    发明人： Shanjen Pan ,  Sameer Pendharkar ,  James R. Todd

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0847 ,  H01L21/266 ,  H01L27/0623 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2029/42388

    摘要： The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

    摘要翻译： 本发明在一个实施例中提供一种晶体管（100）。 晶体管（100）包括半导体衬底（105）上方的掺杂半导体衬底（105）和栅极结构（110），栅极结构（110）具有栅极拐角（125）。 晶体管（100）还包括由掺杂半导体衬底（105）围绕的漏极扩展阱（115）。 漏极扩展阱（115）具有与掺杂半导体衬底（105）相反的掺杂剂类型。 漏极扩展阱（115）还在高掺杂区域（150）之间具有低掺杂区域（145），其中低掺杂区域（155）的边缘基本上与由 门角（125）。 本发明的其他实施例包括制造晶体管（200）和集成电路（300）的方法。

    Methods of fabricating high voltage devices
    48.
    发明申请
    Methods of fabricating high voltage devices 有权
    制造高压器件的方法

    公开(公告)号：US20060286741A1

    公开(公告)日：2006-12-21

    申请号：US11154431

    申请日：2005-06-16

    申请人： Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James Todd

    发明人： Shanjen Pan ,  Sameer Pendharkar ,  Pinghai Hao ,  James Todd

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/0629 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835

    摘要： Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

    摘要翻译： 制造方法和器件包括在电容器形成期间形成的场板。 在半导体衬底中形成隔离结构。 在半导体衬底中形成阱区。 在阱区域中形成漏极延伸区域。 在器件上形成栅极电介质层。 形成用作栅电极和底电容器板的栅极电极层。 对栅极电极和栅极介电层进行图案化以形成栅极结构。 源区和漏区形成在阱区和漏极延伸区内。 形成也用作电容器电介质的硅化物阻挡层。 在阻挡层上形成场板和顶部电容器板。

    Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices
    50.
    发明授权
    Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices 有权
    采用高压器件的低压CMOS集成电路的方法和结构

    公开(公告)号：US07112480B2

    公开(公告)日：2006-09-26

    申请号：US11187472

    申请日：2005-07-22

    申请人： Shanjen Pan ,  James R. Todd ,  Sameer Pendharkar

    发明人： Shanjen Pan ,  James R. Todd ,  Sameer Pendharkar

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7833 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0922

    摘要： A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

    摘要翻译： CMOS集成电路（15A-B-C）包括同一芯片上的相对低功率（124,126）和大功率（132,134）CMOS晶体管。 20V，相对高功率的PMOS器件（134）包括重掺杂的N阱漏极区（70）。 20V，相对高功率的NMOS器件（132）包括在源极（94）和漏极区（96）下面的重掺杂的P型掩埋层（76,78），并跨越P阱栅极（90°F）之间的间隙 ）和相邻的P阱隔离区（46,50）。