公开(公告)号：US20100022086A1

公开(公告)日：2010-01-28

申请号：US12506361

申请日：2009-07-21

申请人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

发明人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

摘要： In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitidation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

摘要翻译： 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 对第一阻挡层的暴露部分进行硝化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。

公开(公告)号：US20080274610A1

公开(公告)日：2008-11-06

申请号：US12112135

申请日：2008-04-30

申请人： Kyung-In Choi ,  Gil-Heyun Choi ,  Hyun-Bae Lee ,  Jong-Won Hong ,  Jong-Myeong Lee

发明人： Kyung-In Choi ,  Gil-Heyun Choi ,  Hyun-Bae Lee ,  Jong-Won Hong ,  Jong-Myeong Lee

IPC分类号： H01L21/285

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76877 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03602 ,  H01L2224/05124 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00014

摘要： Methods of forming a semiconductor device that includes a diffusion barrier film are provided. The diffusion barrier film includes a metal nitride formed by using a MOCVD process and partially treated with a plasma treatment. Thus, a specific resistance of the diffusion barrier film can be decreased, and the diffusion barrier film may have distinguished barrier characteristics.

摘要翻译： 提供了形成包括扩散阻挡膜的半导体器件的方法。 扩散阻挡膜包括通过使用MOCVD工艺形成并通过等离子体处理部分处理的金属氮化物。 因此，可以减小扩散阻挡膜的电阻率，并且扩散阻挡膜可能具有显着的屏障特性。

公开(公告)号：US20070128866A1

公开(公告)日：2007-06-07

申请号：US11671779

申请日：2007-02-06

申请人： Sang-Woo Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Kyung-In Choi

发明人： Sang-Woo Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Kyung-In Choi

IPC分类号： H01L21/44 ,  C23C16/00

CPC分类号： H01L21/76843 ,  H01L21/28562 ,  H01L21/76864

摘要： A method forming a tungsten contact can include forming a contact hole in an interlayer dielectric layer to expose a portion of an underlying silicon based substrate and to form a side wall of the contact hole. A tungsten silicide layer can be formed on at least on the exposed portion of the substrate. A tungsten nitride layer can be conformally formed on a surface of the interlayer dielectric layer, on the tungsten silicide layer and on the side wall. A contact tungsten layer can be formed on the tungsten nitride layer to fill the contact hole. Related apparatus and contacts are also disclosed.

摘要翻译： 形成钨接触的方法可以包括在层间电介质层中形成接触孔以暴露下面的硅基衬底的一部分并形成接触孔的侧壁。 至少在衬底的暴露部分上可以形成硅化钨层。 氮化钨层可以共形地形成在层间电介质层的表面上，硅化钨层和侧壁上。 可以在氮化钨层上形成接触钨层以填充接触孔。 还公开了相关装置和接触。

公开(公告)号：US07189641B2

公开(公告)日：2007-03-13

申请号：US10920482

申请日：2004-08-18

申请人： Sang-Woo Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Kyung-In Choi

发明人： Sang-Woo Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Kyung-In Choi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/28562 ,  H01L21/76864

摘要： A method forming a tungsten contact can include forming a contact hole in an interlayer dielectric layer to expose a portion of an underlying silicon based substrate and to form a side wall of the contact hole. A tungsten silicide layer can be formed on at least on the exposed portion of the substrate. A tungsten nitride layer can be conformally formed on a surface of the interlayer dielectric layer, on the tungsten silicide layer and on the side wall. A contact tungsten layer can be formed on the tungsten nitride layer to fill the contact hole. Related apparatus and contacts are also disclosed.

摘要翻译： 形成钨接触的方法可以包括在层间电介质层中形成接触孔以暴露下面的硅基衬底的一部分并形成接触孔的侧壁。 至少在衬底的暴露部分上可以形成硅化钨层。 氮化钨层可以共形地形成在层间电介质层的表面上，硅化钨层和侧壁上。 可以在氮化钨层上形成接触钨层以填充接触孔。 还公开了相关装置和接触。

公开(公告)号：US06699790B2

公开(公告)日：2004-03-02

申请号：US10035807

申请日：2002-01-04

申请人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

发明人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

IPC分类号： H01L21443

CPC分类号： H01L21/76876 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882

摘要： A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.

摘要翻译： 一种在硅衬底上的绝缘层中具有凹陷区域的半导体器件制造方法，包括以下步骤：在绝缘层的整个表面上沉积阻挡金属，用氧化物层填充该凹陷区域， 去除所述凹陷区域中的氧化物层并暴露所述凹陷区域的阻挡金属，在所述阻挡金属上沉积CVD-Al层，以及在所述CVD-Al层上沉积PVD-Al层，以及 重新流动PVD-Al层。 根据本发明的半导体集成电路的制造方法选择性地去除凹陷区域的外部的阻挡金属以将绝缘层暴露于空气，并沉积CVD-Al层和PVD-Al层，这导致 控制CVD-Al金属的异常生长。

公开(公告)号：US08547747B2

公开(公告)日：2013-10-01

申请号：US13191581

申请日：2011-07-27

申请人： Su-Kyoung Kim ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Su-Kyoung Kim ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： G11C16/04

CPC分类号： H01L29/7926 ,  G11C5/063 ,  G11C16/0483 ,  H01L27/11582

摘要： A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.

摘要翻译： 提供了一种非易失性存储器件，包括由单晶半导体形成的衬底，垂直于衬底延伸的柱状半导体图案，多个栅极电极和与衬底垂直交替堆叠的多个层间电介质层，以及 形成在所述多个栅极电极和所述多个层间电介质层之间的电荷扩展阻挡层。

公开(公告)号：US08476763B2

公开(公告)日：2013-07-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/4763 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  G06F17/50

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US08324055B2

公开(公告)日：2012-12-04

申请号：US13044703

申请日：2011-03-10

申请人： Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Jong-Myeong Lee

发明人： Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76254 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/1203

摘要： A method of manufacturing a buried wiring type substrate comprises implanting hydrogen ions into a single crystalline substrate through a first surface thereof to form an ion implantation region, forming a conductive layer comprising a metal on the first surface of the single crystalline substrate, forming an insulation layer comprising silicon oxide on the conductive layer, bonding the insulation layer to a support substrate to form a preliminary buried wiring type substrate, and separating the single crystalline substrate at the ion implantation region to form a single crystalline semiconductor layer on the conductive layer.

摘要翻译： 一种掩埋布线型衬底的制造方法，包括通过其第一表面将氢离子注入单晶衬底以形成离子注入区，在单晶衬底的第一表面上形成包含金属的导电层，形成绝缘层 在导电层上包含氧化硅的层，将绝缘层粘合到支撑衬底上以形成预埋掩埋布线型衬底，并且在离子注入区域处分离单晶衬底，以在导电层上形成单晶半导体层。

公开(公告)号：US20120193792A1

公开(公告)日：2012-08-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US20120009781A1

公开(公告)日：2012-01-12

申请号：US13240109

申请日：2011-09-22

申请人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

发明人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

摘要： In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

摘要翻译： 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 在第一阻挡层的暴露部分上进行氮化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。