公开(公告)号：US07681154B2

公开(公告)日：2010-03-16

申请号：US11854591

申请日：2007-09-13

申请人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

发明人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5036

摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

摘要翻译： 公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。 第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。 第二半导体芯片包括耦合到输入焊盘的输出焊盘。 调整对象被连接到第一和第二半导体芯片。 主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。 考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型 芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。 将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

公开(公告)号：US07569428B2

公开(公告)日：2009-08-04

申请号：US11525952

申请日：2006-09-25

申请人： Satoshi Isa ,  Satoshi Itaya ,  Mitsuaki Katagiri ,  Fumiyuki Osanai ,  Hiroki Fujisawa

发明人： Satoshi Isa ,  Satoshi Itaya ,  Mitsuaki Katagiri ,  Fumiyuki Osanai ,  Hiroki Fujisawa

IPC分类号： H01L21/82 ,  H01L23/52

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.

摘要翻译： 公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。 该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据 预定的布局。 多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。 所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

公开(公告)号：US20080012107A1

公开(公告)日：2008-01-17

申请号：US11822265

申请日：2007-07-03

申请人： Satoshi Isa ,  Mitsuaki Katagiri ,  Kyoichi Nagata ,  Seiji Narui

发明人： Satoshi Isa ,  Mitsuaki Katagiri ,  Kyoichi Nagata ,  Seiji Narui

IPC分类号： H01L23/02

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.

摘要翻译： 公开了一种半导体存储器件，其中芯片上的焊盘分别焊接到封装的焊球的焊盘上，所述焊盘分别布置在芯片的彼此面对的第一和第二侧上，并且设置在第三侧 的芯片以及。 四组用于数据信号的焊盘分别设置在通过将第一和第二侧划分成四个区域而获得的四个区域上。 用于命令/地址信号的板被布置在第三侧上，从而增加了用于数据信号的接合点的布局空间，并实现了数据信号的布线的均匀性。

公开(公告)号：US20070069362A1

公开(公告)日：2007-03-29

申请号：US11525952

申请日：2006-09-25

申请人： Satoshi Isa ,  Satoshi Itaya ,  Mitsuaki Katagiri ,  Fumiyuki Osanai ,  Hiroki Fujisawa

发明人： Satoshi Isa ,  Satoshi Itaya ,  Mitsuaki Katagiri ,  Fumiyuki Osanai ,  Hiroki Fujisawa

IPC分类号： H01L23/48

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.

摘要翻译： 公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。 该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据 预定的布局。 多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。 所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

公开(公告)号：US20070057380A1

公开(公告)日：2007-03-15

申请号：US11511438

申请日：2006-08-29

申请人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Satoshi Isa ,  Yoji Nishio ,  Seiji Funaba ,  Yukitoshi Hirose

发明人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Satoshi Isa ,  Yoji Nishio ,  Seiji Funaba ,  Yukitoshi Hirose

IPC分类号： H01L23/48

CPC分类号： H05K3/0005 ,  G06F17/5068 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/10545 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.

摘要翻译： 公开了一种考虑半导体封装中所包括的半导体芯片的功率完整性来设计包括半导体封装的半导体器件的方法。 基于关于调整对象的目标信息来计算用于调整目标的目标变量，其中目标变量在频域中被表示，并且调整目标包括半导体封装的一部分。 将目标变量与在频域中表示的预定约束进行比较，以识别有问题的部分，其中有问题的部分对应于目标变量超过预定约束的频率区域。 决定设计指南来解决确定的问题部分。

公开(公告)号：US08164186B2

公开(公告)日：2012-04-24

申请号：US11105546

申请日：2005-04-14

申请人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

发明人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/15311 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/09781 ,  H05K2201/2036 ,  Y02P70/613

摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。

公开(公告)号：US20100295179A1

公开(公告)日：2010-11-25

申请号：US12846120

申请日：2010-07-29

申请人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

发明人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

IPC分类号： H01L23/498

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/15311 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/09781 ,  H05K2201/2036 ,  Y02P70/613

摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。

公开(公告)号：US07119428B2

公开(公告)日：2006-10-10

申请号：US11025634

申请日：2004-12-28

申请人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjo ,  Mitsuaki Katagiri ,  Yuji Watanabe

发明人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjo ,  Mitsuaki Katagiri ,  Yuji Watanabe

IPC分类号： H01L23/22 ,  H01L23/053 ,  H01L21/44

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.

摘要翻译： 提供一种能够在其操作期间降低温度升高的半导体器件。 在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数 的多个半导体元件。

公开(公告)号：US20060081972A1

公开(公告)日：2006-04-20

申请号：US11247215

申请日：2005-10-12

申请人： Mitsuaki Katagiri ,  Hiroya Shimizu ,  Fumiyuki Osanai ,  Yasushi Takahashi ,  Seiji Narui

发明人： Mitsuaki Katagiri ,  Hiroya Shimizu ,  Fumiyuki Osanai ,  Yasushi Takahashi ,  Seiji Narui

IPC分类号： H01L23/48

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L2224/4824 ,  H01L2924/13091 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.

公开(公告)号：US06911683B2

公开(公告)日：2005-06-28

申请号：US10658402

申请日：2003-09-10

申请人： Satoru Konishi ,  Mitsuaki Katagiri ,  Kazumasa Yanagisawa

发明人： Satoru Konishi ,  Mitsuaki Katagiri ,  Kazumasa Yanagisawa

IPC分类号： H01L27/04 ,  G11C7/10 ,  H01L21/82 ,  H01L21/822 ,  H01L23/528 ,  H01L27/10

CPC分类号： H01L23/5286 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor integrated circuit device has a semiconductor substrate with a plurality of pads disposed over a main surface of the substrate along one side thereof. A plurality of input/output cells are disposed corresponding to the plural pads over the main surface of the substrate. An internal circuit forming section is disposed over the main surface of the substrate. Power supply wirings for the internal circuit supply potentials to the internal circuit forming section. The plural input/output cells include signal cells and power supply cells for internal circuit respectively. Signal pads are disposed corresponding to the signal cells and electrically connected the signal cells. Power supply pads for the internal circuit are respectively disposed corresponding to the power supply cells and electrically connected to the power supply cells and the power supply wirings.

摘要翻译： 半导体集成电路器件具有半导体衬底，其多个焊盘沿着衬底的主表面沿其一侧设置在主表面上。 多个输入/输出单元相对于衬底的主表面上的多个焊盘设置。 内部电路形成部分设置在基板的主表面上。 用于内部电路的电源配线向内部电路形成部分供电。 多个输入/输出单元分别包括用于内部电路的信号单元和电源单元。 信号焊盘对应于信号单元布置并且电连接信号单元。 用于内部电路的电源焊盘分别对应于电源单元设置并电连接到电源单元和电源配线。