公开(公告)号：US09390932B2

公开(公告)日：2016-07-12

申请号：US14617937

申请日：2015-02-10

Applicant: INTEL CORPORATION

Inventor： Patricio E. Romero ,  Scott B. Clendenning

IPC: H01L29/06 ,  H01L21/285 ,  H01L29/78 ,  H01L29/786 ,  H01L29/49 ,  H01L29/45 ,  H01L21/768 ,  C23C16/30 ,  C23C16/42 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/04 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28556 ,  C23C16/30 ,  C23C16/42 ,  H01L21/28506 ,  H01L21/28562 ,  H01L21/28575 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L29/04 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 Å thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.

Abstract translation: 本发明的实施方案提供了通过ALD（原子层沉积）和/或CVD（化学气相沉积）工艺形成包含正电性金属的层的方法，包括一种或多种正电性金属的层以及包含一种或多种正电性金属的层的半导体器件 。 在本发明的实施方案中，这些层是薄的或超薄的（小于100埃的膜）和/或保形膜。 另外提供的是晶体管器件，金属互连和包括包含一种或多种正电性金属的金属层的计算器件。

公开(公告)号：US20150243508A1

公开(公告)日：2015-08-27

申请号：US14617937

申请日：2015-02-10

Applicant: INTEL CORPORATION

Inventor： Patricio E. Romero ,  Scott B. Clendenning

IPC: H01L21/285 ,  H01L29/51 ,  H01L29/49 ,  H01L29/16 ,  H01L29/161 ,  H01L21/768 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/201

CPC classification number: H01L21/28556 ,  C23C16/30 ,  C23C16/42 ,  H01L21/28506 ,  H01L21/28562 ,  H01L21/28575 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L29/04 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 Å thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.

Abstract translation: 本发明的实施方案提供了通过ALD（原子层沉积）和/或CVD（化学气相沉积）工艺形成包含正电性金属的层的方法，包括一种或多种正电性金属的层以及包含一种或多种正电性金属的层的半导体器件 。 在本发明的实施方案中，这些层是薄的或超薄的（小于100埃的膜）和/或保形膜。 另外提供的是晶体管器件，金属互连和包括包含一种或多种正电性金属的金属层的计算器件。

公开(公告)号：US20240222475A1

公开(公告)日：2024-07-04

申请号：US18148617

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young ,  John J. Plombon ,  Scott B. Clendenning ,  Mahendra DC

IPC: H01L29/66 ,  H01F10/12 ,  H01F10/193 ,  H01F10/32 ,  H10N52/01

CPC classification number: H01L29/66984 ,  H01F10/12 ,  H01F10/1933 ,  H01F10/329 ,  H10N52/01

Abstract: Technologies for high-performance magnetoelectric spin-orbit (MESO) logic structures are disclosed. In the illustrative embodiment, the spin-orbit coupling layer of a MESO logic structure is a high-entropy perovskite. The use of a high-entropy perovskite provides versatility through tunability, as there is a wide range of possible combinations. Additional layers of the MESO logic structure may also be perovskites, such as the magnetoelectric layer and ferromagnetic layer. The various perovskite layers may be epitaxially compatible, allowing for growth of high-quality layers.

公开(公告)号：US20240113220A1

公开(公告)日：2024-04-04

申请号：US17958094

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Uygar E. Avci ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Jason C. Retasket ,  Shriram Shivaraman ,  Dominique A. Adams ,  Carly Rogan ,  Punyashloka Debashis ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Sudarat Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

CPC classification number: H01L29/78391 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7606

Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

公开(公告)号：US20240113212A1

公开(公告)日：2024-04-04

申请号：US17956296

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Hai Li ,  Arnab Sen Gupta ,  Gauri Auluck ,  I-Cheng Tung ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Punyashloka Debashis

IPC: H01L29/775 ,  H01L21/02 ,  H01L21/465 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

公开(公告)号：US20240097031A1

公开(公告)日：2024-03-21

申请号：US17947071

申请日：2022-09-16

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Rachel A. Steinhardt ,  Brandon Holybee ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Ian Alexander Young ,  Raseong Kim ,  Carly Rogan ,  Dominique A. Adams ,  Arnab Sen Gupta ,  Marko Radosavljevic ,  Scott B. Clendenning ,  Gauri Auluck ,  Hai Li ,  Matthew V. Metz ,  Tristan A. Tronic ,  I-Cheng Tung

IPC: H01L29/78 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L29/516

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

公开(公告)号：US20230411390A1

公开(公告)日：2023-12-21

申请号：US17842462

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Ande Kitamura ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Rachel A. Steinhardt ,  Scott B. Clendenning ,  Sudarat Lee ,  Uygar E. Avci ,  Chelsey Dorow

IPC: H01L27/092 ,  H03K19/0185 ,  H01L29/26 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/092 ,  H03K19/018571 ,  H01L29/26 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/5283

Abstract: In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).

公开(公告)号：US20230197860A1

公开(公告)日：2023-06-22

申请号：US17560069

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Kirby Maxey ,  Chelsey Dorow ,  Sudarat Lee ,  Kevin O'Brien ,  Ashish V. Penumatcha ,  Scott B. Clendenning ,  Uygar Avci ,  Matthew Metz

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/66969 ,  H01L29/4908

Abstract: A metal chalcogenide material layer of lower quality provides a transition between a metal chalcogenide material layer of higher quality and a gate insulator material that separates the metal chalcogenide material layers from a gate electrode of a metal-oxide semiconductor field effect transistor (MOSFET) structure. Gate insulator material may be more readily initiated and/or or precisely controlled to a particular thickness when formed on lower quality metal chalcogenide material. Accordingly, such a material stack may be integrated into a variety of transistor structures, including multi-gate, multi-channel nanowire or nanosheet transistor structures.

公开(公告)号：US20230197836A1

公开(公告)日：2023-06-22

申请号：US17557128

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Carl Hugo Naylor ,  Christopher J. Jezewski ,  Jeffery D. Bielefeld ,  Jiun-Ruey Chen ,  Ramanan V. CHEBIAM ,  Mauro J. Kobrinsky ,  Matthew V. Metz ,  Scott B. Clendenning ,  Sudurat Lee ,  Kevin P. O'Brien ,  Kirby Kurtis Maxey ,  Ashish Verma Penumatcha ,  Chelsey Jane Dorow ,  Uygar E. Avci

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7606 ,  H01L29/0665 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02568 ,  H01L29/401 ,  H01L29/66969

Abstract: Described herein are integrated circuit devices with conductive regions formed from MX or MAX materials. MAX materials are layered, hexagonal carbides and nitrides that include an early transition metal (M) and an A group element (A). MX materials remove the A group element. MAX and MX materials are highly conductive, and their two-dimensional layer structure allows very thin layers to be formed. MAX or MX materials can be used to form several conductive elements of IC circuits, including contacts, interconnects, or liners or barrier regions for contacts or interconnects.

公开(公告)号：US20230197602A1

公开(公告)日：2023-06-22

申请号：US17560085

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Elijah Karpov ,  Miriam Reshotko ,  Scott B. Clendenning ,  Jiun-Ruey Chen ,  Matthew Metz

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53238 ,  H01L23/53266

Abstract: Adjacent interconnect lines are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within one level of interconnect metallization. Short and tall interconnect via openings are landed on the vertically staggered interconnect lines. Cap material selectively deposited upon upper ones of the staggered interconnect lines limits over etch of the short vias while the tall vias are advanced toward lower ones of the staggered interconnect lines. The via openings of differing depth may be filled, for example with a single damascene metallization process that defines a co-planar top surface for all via metallization over the staggered, vertically spaced interconnect lines.