公开(公告)号：US20160329431A1

公开(公告)日：2016-11-10

申请号：US15212991

申请日：2016-07-18

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/786 ,  H01L21/768 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/78618 ,  H01L21/76805 ,  H01L21/76886 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

公开(公告)号：US20160056156A1

公开(公告)日：2016-02-25

申请号：US14779936

申请日：2013-06-20

Applicant: INTEL CORPORATION

Inventor： TAHIR GHANI ,  SALMAN LATIF ,  CHANAKA D. MUNASINGHE

IPC: H01L27/092 ,  H01L21/225 ,  H01L29/08 ,  H01L21/3105 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L27/0924 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/31051 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66803

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

Abstract translation: 描述了具有掺杂亚鳍片区域的非平面半导体器件和制造具有掺杂子鳍片区域的非平面半导体器件的方法。 例如，制造半导体结构的方法包括在半导体衬底上形成多个半导体鳍片。 固态掺杂剂源层形成在半导体衬底之上，与多个半导体鳍片保形。 在固态掺杂剂源层上形成介电层。 电介质层和固态掺杂剂源层在多个半导体鳍片的顶表面下方凹陷到大致相同的水平面，使多个半导体鳍片中的每一个的多个半导体鳍片中的每一个的突出部分暴露在多个半导体鳍片 半导体鳍片。 该方法还涉及将掺杂剂从固体掺杂剂源层驱动到多个半导体鳍片中的每一个的子鳍片区域中。

公开(公告)号：US20200286996A1

公开(公告)日：2020-09-10

申请号：US16876528

申请日：2020-05-18

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  ARAVIND S. KILLAMPALLI ,  MARK R. BRAZIER ,  JAYA P. GUPTA

IPC: H01L29/10 ,  H01L29/775 ,  H01L21/30 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06

Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

公开(公告)号：US20200006488A1

公开(公告)日：2020-01-02

申请号：US16020361

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  BISWAJEET GUHA ,  ANUPAMA BOWONDER ,  ANAND S. MURTHY ,  TAHIR GHANI ,  STEPHEN M. CEA

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66

Abstract: Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth.

公开(公告)号：US20190189794A1

公开(公告)日：2019-06-20

申请号：US16283756

申请日：2019-02-23

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  GLENN A. GLASS ,  TAHIR GHANI ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  MATTHEW V. METZ ,  HAROLD W. KENNEL

IPC: H01L29/78 ,  H01L29/12 ,  H01L29/775 ,  H01L29/66 ,  H01L27/088 ,  H01L29/205 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L21/02241 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/125 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/775

Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.

公开(公告)号：US20190189785A1

公开(公告)日：2019-06-20

申请号：US16326845

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  SEUNG HOON SUNG ,  BENJAMIN CHU-KUNG ,  TAHIR GHANI

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66803 ,  H01L29/10 ,  H01L29/1025 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851

Abstract: Integrated circuit transistor structures are disclosed that include a gate structure that is lattice matched to the underlying channel. In particular, the gate dielectric is lattice matched to the underlying semiconductor channel material, and in some embodiments, so is the gate electrode. In an example embodiment, single crystal semiconductor channel material and single crystal gate dielectric material that are sufficiently lattice matched to each other are epitaxially deposited. In some cases, the gate electrode material may also be a single crystal material that is lattice matched to the semiconductor channel material, thereby allowing the gate electrode to impart strain on the channel via the also lattice matched gate dielectric. A gate dielectric material that is lattice matched to the channel material can be used to reduce interface trap density (Dit). The techniques can be used in both planar and non-planar (e.g., finFET and nanowire) metal oxide semiconductor (MOS) transistor architectures.

公开(公告)号：US20190097055A1

公开(公告)日：2019-03-28

申请号：US16081572

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  TAHIR GHANI ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  MATTHEW V. METZ ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L29/7853 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818

Abstract: Techniques are disclosed for forming a beaded fin transistor. As will be apparent in light of this disclosure, a transistor including a beaded fin configuration may be formed by starting with a multilayer finned structure, and then selectively etching one or more of the layers to form at least one necked (or relatively narrower) portion, thereby forming a beaded fin structure. The beaded fin transistor configuration has improved gate control over a finned transistor configuration having the same top down area or footprint, because the necked/narrower portions increase gate surface area as compared to a non-necked finned structure, such as finned structures used in finFET devices. Further, because the beaded fin structure remains intact (e.g., as compared to a gate-all-around (GAA) transistor configuration where nanowires are separated from each other), the parasitic capacitance problems caused by GAA transistor configurations are mitigated or eliminated.

公开(公告)号：US20190081233A1

公开(公告)日：2019-03-14

申请号：US16073687

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： KEVIN J. LEE ,  OLEG GOLONZKA ,  TAHIR GHANI ,  RUTH A. BRAIN ,  YIH WANG

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/14 ,  H01L43/08 ,  H01L43/10

Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.

公开(公告)号：US20190043993A1

公开(公告)日：2019-02-07

申请号：US16076550

申请日：2016-03-11

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  WILLY RACHMADY ,  GILBERT DEWEY ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8252

Abstract: Techniques are disclosed for forming transistors including one or more group III-V semiconductor material nanowires using sacrificial group IV semiconductor material layers. In some cases, the transistors may include a gate-all-around (GAA) configuration. In some cases, the techniques may include forming a replacement fin stack that includes group III-V material layer (such as indium gallium arsenide, indium arsenide, or indium antimonide) formed on a group IV material buffer layer (such as silicon, germanium, or silicon germanium), such that the group IV buffer layer can be later removed using a selective etch process to leave the group III-V material for use as a nanowire in a transistor channel. In some such cases, the group III-V material layer may be grown pseudomorphically to the underlying group IV material, so as to not form misfit dislocations. The techniques may be used to form transistors including any number of nanowires.

公开(公告)号：US20180248015A1

公开(公告)日：2018-08-30

申请号：US15754874

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  MARK R. BRAZIER ,  ANAND S. MURTHY ,  TAHIR GHANI ,  OWEN Y. LOH

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/775 ,  H01L29/06 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/517 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated include the interface between the semiconductor channel and the gate dielectric and/or the interface between the sub-channel semiconductor material and isolation material. For example, an aluminum oxide (also referred to as alumina) layer may be used to passivate channel/gate interfaces where the channel material includes silicon germanium, germanium, or a III-V material. The techniques can be used to reduce the interface trap density at the channel/gate interface and the techniques can also be used to passivate the channel/gate interface in both gate first and gate last process flows. The techniques may also include an additional passivation layer at the sub-channel/isolation interface to, for example, avoid incurring additional parasitic capacitance penalty.