公开(公告)号：US09768110B2

公开(公告)日：2017-09-19

申请号：US15060685

申请日：2016-03-04

Applicant: International Business Machines Corporation

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01R43/00 ,  H01L23/522 ,  H01L23/528 ,  H04L9/32 ,  H05K1/02 ,  H01L21/027 ,  H01L21/321 ,  H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

公开(公告)号：US09721854B2

公开(公告)日：2017-08-01

申请号：US13705213

申请日：2012-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L21/66 ,  G01R31/02 ,  G01R31/26 ,  G01R31/28

CPC classification number: H01L22/14 ,  G01R31/024 ,  G01R31/2644 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.

公开(公告)号：US09691718B2

公开(公告)日：2017-06-27

申请号：US15080650

申请日：2016-03-25

Applicant: International Business Machines Corporation

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L29/66 ,  H01L23/00 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L23/576 ,  H01L21/28158 ,  H01L21/823462 ,  H01L23/573 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42368 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A physical unclonable function (PUF) semiconductor device includes a semiconductor substrate extending along a first direction to define a length and a second direction opposite the first direction to define a thickness. At least one pair of semiconductor structures is formed on the semiconductor substrate. The semiconductor structures include a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first gate dielectric layer having a first shape that defines a first threshold voltage. The second semiconductor structure includes a second gate dielectric layer having a second dielectric shape that is reversely arranged with respect to the first shape and that defines a second threshold voltage different from the first threshold voltage.

公开(公告)号：US09536829B2

公开(公告)日：2017-01-03

申请号：US14483258

申请日：2014-09-11

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/58 ,  H01L23/525 ,  H01L23/48

CPC classification number: H01L23/5256 ,  H01L23/481 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An method including forming a back end of the line (BEOL) wiring portion directly on top of a semiconductor base portion, the BEOL wiring portion including a plurality of layers of a metallic material and a dielectric material and excluding a semiconductor material, forming a through-substrate via through the BEOL wiring portion and the semiconductor base portion, forming an electronic fuse in the BEOL wiring portion adjacent to the through-substrate via, and forming a guard ring in the BEOL wiring portion surrounding the through-substrate via and the electronic fuse in the BEOL wiring portion, the through-substrate via in the semiconductor base portion being free from the guard ring.

Abstract translation: 一种包括在半导体基部的顶部直接形成线（BEOL）布线部分的后端的方法，所述BEOL布线部分包括多层金属材料和电介质材料，并且不包括半导体材料，形成通孔 - 通过BEOL布线部分和半导体基底部衬底通孔，在与穿通基板通孔相邻的BEOL布线部分中形成电子熔断器，并且在围绕贯穿基板通孔的BEOL布线部分中形成保护环，并且电子 在BEOL布线部分中熔断，半导体基底部分中的贯通基板通孔没有保护环。

公开(公告)号：US09536779B2

公开(公告)日：2017-01-03

申请号：US14721440

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

Abstract translation: 一种形成集成电路器件的布线结构的方法包括在层间电介质（ILD）层内形成第一金属线，并在与第一金属线相邻的ILD层中形成第二金属线; 掩蔽所述第一和第二金属线的选定区域; 以周期性间隔选择性地在第一和第二金属线的暴露区域上电镀金属帽区域，使得单个金属线的相邻金属帽区域之间的间隔对应于临界长度L，在该临界长度L处，背应力梯度平衡电迁移力 在各个金属线上，以抑制电子的质量传递; 并且其中所述第一金属线的金属帽区域沿着共同的纵向轴线相对于所述第二金属线的金属帽区域以交错位置形成。

公开(公告)号：US09524930B2

公开(公告)日：2016-12-20

申请号：US14167240

申请日：2014-01-29

Applicant: International Business Machines Corporation

Inventor： Oleg Gluschenkov ,  Yunsheng Song ,  Tso-Hui Ting ,  Ping-Chuan Wang

IPC: H01L21/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/48 ,  H01L25/065 ,  H05K1/02 ,  H01L21/66 ,  H01L23/00 ,  H05K1/14

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L22/20 ,  H01L23/13 ,  H01L23/481 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1403 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/15311 ,  H05K1/0286 ,  H05K1/142 ,  H05K2201/2018 ,  H05K2203/1572 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Abstract translation: 模块化插入器包括多个插入器单元，其被组合以提供两个半导体芯片之间的完整的电连接。 多个插入单元中的至少一些可以被具有替代配置的其它插入单元替代，以便能够通过模块化插入器选择要连接的半导体芯片的不同功能部件。 连接到位于相邻插入单元周围的导电金属焊盘和半导体芯片的上部或下部的结合结构可以在相邻插入单元之间提供电连接。 可以通过在衬底中形成贯穿衬底通孔（TSV）来形成插入器单元，在衬底上形成图案化的导电结构，并将衬底切割成插入层。

公开(公告)号：US20160315138A1

公开(公告)日：2016-10-27

申请号：US14692881

申请日：2015-04-22

Applicant: International Business Machines Corporation

Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L49/02

CPC classification number: H01L28/92 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629

Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

Abstract translation: 提供了基于半导体纳米棒阵列的高密度电容器结构。 高密度电容器结构可以是多个电容器，其中每个半导体纳米棒用作多个电容器中的一个电容器的底部电极，或大面积金属 - 绝缘体金属（MIM）电容器，其中半导体纳米棒 用作随后形成的MIM电容器的底部电极的支撑结构。

公开(公告)号：US20160079166A1

公开(公告)日：2016-03-17

申请号：US14483258

申请日：2014-09-11

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/525 ,  H01L21/3205 ,  H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/58

CPC classification number: H01L23/5256 ,  H01L23/481 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An method including forming a back end of the line (BEOL) wiring portion directly on top of a semiconductor base portion, the BEOL wiring portion including a plurality of layers of a metallic material and a dielectric material and excluding a semiconductor material, forming a through-substrate via through the BEOL wiring portion and the semiconductor base portion, forming an electronic fuse in the BEOL wiring portion adjacent to the through-substrate via, and forming a guard ring in the BEOL wiring portion surrounding the through-substrate via and the electronic fuse in the BEOL wiring portion, the through-substrate via in the semiconductor base portion being free from the guard ring.

Abstract translation: 一种包括在半导体基部的顶部直接形成线（BEOL）布线部分的后端的方法，所述BEOL布线部分包括多层金属材料和电介质材料，并且不包括半导体材料，形成通孔 - 通过BEOL布线部分和半导体基底部衬底通孔，在与穿通基板通孔相邻的BEOL布线部分中形成电子熔断器，并且在围绕贯穿基板通孔的BEOL布线部分中形成保护环，并且电子 在BEOL布线部分中熔断，半导体基底部分中的贯通基板通孔没有保护环。

公开(公告)号：US09281236B2

公开(公告)日：2016-03-08

申请号：US14718128

申请日：2015-05-21

Applicant: International Business Machines Corporation

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H03K19/00 ,  H01L21/768 ,  H01L23/535 ,  H01L23/00 ,  H03K19/003 ,  H03K19/0948

CPC classification number: H01L21/76802 ,  G06F21/73 ,  G09C1/00 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/535 ,  H01L23/564 ,  H01L23/57 ,  H01L2924/0002 ,  H03K19/003 ,  H03K19/0948 ,  H04L9/3278 ,  H04L2209/12 ,  H01L2924/00

Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification.

公开(公告)号：US20150380326A1

公开(公告)日：2015-12-31

申请号：US14320598

申请日：2014-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Mukta G. Farooq ,  John A. Griesemer ,  Chandrasekaran Kothandaraman ,  John M. Safran ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L21/66 ,  G01R31/08 ,  H01L23/48

CPC classification number: G01R31/08 ,  G01R31/2856 ,  G01R31/2858 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Abstract translation: 诸如晶片，芯片，IC，设计结构等的结构包括硅通孔（TSV）和电迁移（EM）监视器。 TSV完全延伸穿过半导体芯片，并且EM监测器包括围绕TSV周边近似排列的多个EM电线。 EM测试方法包括强制电流通过紧邻TSV周界布置的EM监测器接线，测量EM监测器接线两端的电阻降，确定在EM监测器接线和TSV之间是否存在电短路 测量的电阻，和/或确定由于TSV引起的接近效应，EM监测布线内是否存在早期电开路或电阻增加。