公开(公告)号：US20180337284A1

公开(公告)日：2018-11-22

申请号：US16034576

申请日：2018-07-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John B. Campi, JR. ,  Robert J. Gauthier, JR. ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/265 ,  H01G4/33 ,  H01G4/30 ,  H01G4/228 ,  H01G4/14 ,  H01G4/005 ,  B32B27/36 ,  B32B27/34 ,  B32B27/32 ,  B32B27/30 ,  B32B27/28 ,  B32B27/08 ,  B32B27/00 ,  B32B7/02 ,  B32B3/08 ,  B29C47/56 ,  B29C47/06 ,  B29C37/00 ,  B29K23/00 ,  B29L31/34 ,  B29L9/00 ,  B29K507/04 ,  B29K105/16

摘要： A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

公开(公告)号：US10037895B2

公开(公告)日：2018-07-31

申请号：US14882548

申请日：2015-10-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Robert R. Robison

IPC分类号： H01L23/62 ,  H01L21/324 ,  H01L27/02 ,  H01L29/866 ,  H01L29/861

CPC分类号： H01L21/324 ,  H01L27/0255 ,  H01L29/8611 ,  H01L29/866

摘要： Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

公开(公告)号：US09881810B2

公开(公告)日：2018-01-30

申请号：US14154273

申请日：2014-01-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Robert R. Robison

IPC分类号： H01L21/324 ,  H01L27/02 ,  H01L29/866 ,  H01L29/861

CPC分类号： H01L21/324 ,  H01L27/0255 ,  H01L29/8611 ,  H01L29/866

摘要： Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

公开(公告)号：US09818542B2

公开(公告)日：2017-11-14

申请号：US14882800

申请日：2015-10-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC分类号： H01L21/8234 ,  H01G4/30 ,  B29C37/00 ,  B29C47/06 ,  H01G4/005 ,  H01G4/14 ,  H01G4/228 ,  H01G4/33 ,  B29C47/56 ,  B32B27/00 ,  B32B7/02 ,  B32B27/08 ,  B32B27/28 ,  B32B27/30 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B3/08 ,  B29K23/00 ,  B29K105/16 ,  B29K507/04 ,  B29L9/00 ,  B29L31/34

CPC分类号： H01L29/7856 ,  B29C37/0025 ,  B29C47/065 ,  B29C47/56 ,  B29K2023/12 ,  B29K2105/16 ,  B29K2507/04 ,  B29K2995/0005 ,  B29K2995/0007 ,  B29L2009/003 ,  B29L2009/005 ,  B29L2031/34 ,  B32B3/08 ,  B32B7/02 ,  B32B27/00 ,  B32B27/08 ,  B32B27/28 ,  B32B27/306 ,  B32B27/308 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B2262/106 ,  B32B2264/105 ,  B32B2264/12 ,  B32B2270/00 ,  B32B2274/00 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/206 ,  B32B2307/518 ,  B32B2307/732 ,  B32B2457/16 ,  H01G4/005 ,  H01G4/14 ,  H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7851 ,  H01L2029/7858

摘要： A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

公开(公告)号：US20170133839A1

公开(公告)日：2017-05-11

申请号：US15398871

申请日：2017-01-05

申请人： International Business Machines Corporation

发明人： James P. Di Sarro ,  Robert J. Gauthier, JR. ,  Nathan D. Jack ,  JunJun Li ,  Souvick Mitra

IPC分类号： H02H9/00 ,  H03K17/687 ,  H02H9/04

摘要： An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

公开(公告)号：US09391065B1

公开(公告)日：2016-07-12

申请号：US14753628

申请日：2015-06-29

申请人： International Business Machines Corporation

发明人： Robert J. Gauthier, Jr. ,  Tom C. Lee ,  You Li ,  Rahul Mishra ,  Souvick Mitra ,  Andreas Scholze

IPC分类号： H01L29/66 ,  H01L27/12 ,  H01L23/495 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78

CPC分类号： H01L27/0255 ,  H01L27/0266 ,  H01L27/027 ,  H01L27/0288 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42372 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7855 ,  H01L2029/7858

摘要： Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

摘要翻译： 场效应二极管结构使用横截面为L形的接合结构（从平面部分延伸的翅片）。 阳极位于翅片的顶面，阴极位于平面部分的端面。 翅片和平面部分的垂直度导致阳极和阴极彼此垂直。 第一栅极绝缘体在顶表面和平面部分之间接触翅片。 第一栅极导体接触第一栅极绝缘体，并且第一栅极绝缘体位于第一栅极导体与鳍的表面之间。 另外，第二栅极绝缘体接触端面和鳍之间的平面部分。 第二栅极导体与第二栅极绝缘体接触，第二栅极绝缘体位于第二栅极导体与平面部分的表面之间。

公开(公告)号：US09059278B2

公开(公告)日：2015-06-16

申请号：US13959777

申请日：2013-08-06

申请人： International Business Machines Corporation

发明人： John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816 ,  H01L29/7835

摘要： Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.

摘要翻译： 公开了半导体结构。 每个半导体结构可以包括衬底和在衬底上的至少一个横向双扩散金属氧化物半导体场效应晶体管（LDMOSFET）。 每个LDMOSFET可以具有完全耗尽的深漏极漂移区域（即完全耗尽的深度镇流电阻器区域），用于提供相对较高的阻塞电压。 公开了漏极漂移区域的不同配置，并且这些不同的配置也可以作为LDMOSFET的导电类型的函数而变化。 另外，每个半导体结构可以包括位于LDMOSFET下方的隔离带以及围绕LDMOSFET横向地定位并且垂直延伸到隔离带的隔离阱，使得LDMOSFET与衬底的下部分和任何相邻器件电隔离 底物。

公开(公告)号：US08912625B2

公开(公告)日：2014-12-16

申请号：US14053986

申请日：2013-10-15

申请人： International Business Machines Corporation

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L27/02 ,  H01L27/12 ,  H01L29/861 ,  G06F17/50 ,  H01L29/74 ,  H01L29/66

CPC分类号： H01L27/0255 ,  G06F17/5022 ,  G06F17/5045 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/6609 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/861

摘要： Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.

摘要翻译： 在SOI工艺中具有减小的结面积的器件结构，制造器件结构的方法以及横向二极管的设计结构。 器件结构包括位于器件区域中并与阳极和阴极之间的p-n结相交的一个或多个电介质区域，例如STI区域。 可以使用浅沟槽隔离技术形成的电介质区域用于在p-n结和阳极侧向间隔的位置处减小p-n结相对于阴极宽度区域的宽度。 介质区域的宽度差和存在产生不对称二极管结构。 由电介质区域占据的器件区域的体积被最小化以保持阴极和阳极的体积。

公开(公告)号：US20140342510A1

公开(公告)日：2014-11-20

申请号：US14450612

申请日：2014-08-04

申请人： International Business Machines Corporation

发明人： Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher Stephen Putnam

IPC分类号： H01L21/8249 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/02

CPC分类号： H01L21/8249 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0266 ,  H01L27/0629 ,  H01L27/0924 ,  H01L29/6609 ,  H01L29/66371 ,  H01L29/66795

摘要： Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.

摘要翻译： 本公开的方面提供了鳍状场效应晶体管（FinFET）工艺技术及其形成方法中的双重静电放电（ESD）保护器件。 在一个实施例中，双ESD保护器件包括：体硅衬底; 形成在本体硅衬底上的浅沟槽隔离（STI）区域; 位于STI区域上方的第一ESD器件; 以及位于所述STI区域下方的第二ESD器件，其中所述第一ESD器件在所述STI区域之上传导电流，并且所述第二ESD器件在所述STI区域之下传导电流。

公开(公告)号：US11141902B2

公开(公告)日：2021-10-12

申请号：US16452836

申请日：2019-06-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC分类号： H01L29/78 ,  B29C48/49 ,  H01L29/66 ,  B29C48/21 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01G4/20 ,  H01L29/08 ,  B29C37/00 ,  B32B3/08 ,  B32B7/02 ,  B32B27/00 ,  B32B27/08 ,  B32B27/28 ,  B32B27/30 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  H01G4/005 ,  H01G4/14 ,  H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L27/088 ,  B29K23/00 ,  B29K105/16 ,  B29K507/04 ,  B29L9/00 ,  B29L31/34

摘要： A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.