公开(公告)号：US20170288177A1

公开(公告)日：2017-10-05

申请号：US15627076

申请日：2017-06-19

Applicant: Micron Technology, Inc.

Inventor： Ai Chie Wang ,  Choon Kuan Lee ,  Chin Hui Chong ,  Wuu Yean Tay

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/495 ,  H01L23/49506 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers.

公开(公告)号：US09640458B2

公开(公告)日：2017-05-02

申请号：US14470831

申请日：2014-08-27

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Dalson Ye ,  Chin Hui Chong ,  Choon Kuan Lee ,  Wang Lai Lee ,  Roslan Bin Said

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  H01L23/12 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L25/11

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/00 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16055 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

公开(公告)号：US20150041204A1

公开(公告)日：2015-02-12

申请号：US14525787

申请日：2014-10-28

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Choon Kuan Lee ,  David J. Corisis

IPC: H01L23/495

CPC classification number: H01L23/4951 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49171 ,  H01L2224/73207 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49169 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant.

Abstract translation: 公开了具有引线框架的微电子封装，包括配置用于堆叠管芯封装的引线框架，以及相关系统和方法。 根据一个实施例的系统包括具有电耦合到引线框架键合位置的第一封装焊接位置的支撑构件。 微电子管芯可以由支撑构件承载并电耦合到第一封装的粘结位置。 引线框架可以附接到引线框架结合位置，以便在裸片定位在引线框架和支撑构件之间的同时延伸到微电子模具附近。 引线框架可以包括背离第一封装焊接位置的第二封装焊接位置。 密封剂可以至少部分地围绕引线框架和微电子管芯，其中第一和第二封装结合位置可从密封剂外部接近。

公开(公告)号：US20130341805A1

公开(公告)日：2013-12-26

申请号：US14011138

申请日：2013-08-27

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Dalson Ye ,  Chin Hui Chong

IPC: H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3114 ,  H01L24/48 ,  H01L25/00 ,  H01L25/043 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/10 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4382 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.

公开(公告)号：US20130127027A1

公开(公告)日：2013-05-23

申请号：US13747116

申请日：2013-01-22

Applicant: Micron Technology, Inc.

Inventor： Ai Chie Wang ,  Choon Kuan Lee ,  Chin Hui Chong ,  Wuu Yean Tay

IPC: H01L23/495

CPC classification number: H01L23/495 ,  H01L23/49506 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers.

Abstract translation: 公开了适用于微电子器件封装的预封装引线框架。 单独的引线框架可以包括一组多个引线并排布置，其中相邻引线彼此间隔开相应的间隙。 封装化合物至少部分地封装该组引线指而不封装微电子器件。 封装化合物通常可以填充两个相邻引线指之间的多个间隙。

公开(公告)号：US20230395569A1

公开(公告)日：2023-12-07

申请号：US18202249

申请日：2023-05-25

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Hari Giduturi ,  Yeon-Chang Hahm

IPC: H01L25/065 ,  H10B80/00 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L2924/1431 ,  H01L23/528 ,  H01L24/08 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2224/08112 ,  H01L2224/0903 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H10B80/00

Abstract: Semiconductor devices, such as memory devices, and associated systems and methods, are disclosed herein. A representative memory device includes a substrate including circuitry, back-end contacts electrically coupled to the circuitry, and front-end contacts. The front-end contacts are configured to receive electrical signals from an external device via a front-end interface. Individual ones of the front-end contacts are electrically coupled to and aligned along an axis with corresponding ones of the back-end contacts.

公开(公告)号：US20230378129A1

公开(公告)日：2023-11-23

申请号：US17750225

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48221 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49177

Abstract: A semiconductor package including a package substrate with an upper surface, a controller, and a die stack. The controller and the die stack are at the upper surface. The die stack includes a shingled sub-stack of semiconductor dies, a reverse-shingled sub-stack of semiconductor dies, and a bridging chip. The bridging chip is bonded between the shingled sub-stack and the reverse-shingled sub-stack, and has an internal trace. A first wire segment is bonded between the controller and a first end of the bridging chip, and a second wire segment is bonded between a second end of the bridging chip and each semiconductor die of the shingled sub-stack. The internal trace electrically couples the first and second wire segments. Additionally, a third wire segment is bonded between the controller and each semiconductor die of the reverse-shingled sub-stack.

公开(公告)号：US20230378128A1

公开(公告)日：2023-11-23

申请号：US17750200

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48221 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49177

Abstract: A semiconductor package having a package substrate including an upper surface, a controller, a first die stack, and a second die stack. The controller, the first die stack, and the second die stack are at the upper surface. The first die stack includes a first shingled sub-stack and a first reverse-shingled sub-stack. The first die stack also includes a first bridging chip between the first shingled and reverse-shingled sub-stacks. The second die stack similarly includes a second shingled sub-stack and a second reverse-shingled sub-stack. The second die stack also includes a second bridging chip bonded to the top of the second reverse-shingled sub-stack. At least a portion of a bottom semiconductor die of the first reverse-shingled sub-stack is vertically aligned with a semiconductor die of the second shingled sub-stack and a semiconductor die of the second reverse-shingled sub-stack.

公开(公告)号：US11710722B2

公开(公告)日：2023-07-25

申请号：US17233129

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Chin Hui Chong ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06572

Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

公开(公告)号：US20230056648A1

公开(公告)日：2023-02-23

申请号：US17982397

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L23/48 ,  H01L27/08 ,  H01L49/02 ,  H01L23/498

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.