公开(公告)号：US20140162412A1

公开(公告)日：2014-06-12

申请号：US14180567

申请日：2014-02-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chin Hui Chong ,  David J. Corisis ,  Choon Kuan Lee

IPC: H01L21/48 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L21/4857 ,  H01L23/50 ,  H01L24/82 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at least partially within an opening in the interposer and operatively coupling an integrated circuit to the interposer. A method is also disclosed which includes obtaining an interposer comprising a dielectric material, forming an opening in the interposer and forming a capacitor that is positioned at least partially within the opening.

Abstract translation: 公开了一种包括插入器的至少一个电容器，至少部分地形成在插入器中形成的开口内的至少一个电容器和可操作地耦合到插入器的集成电路。 公开了一种方法，其包括获得具有至少部分地在插入器中的开口内形成的至少一个电容器并且将集成电路可操作地耦合到插入器的插入器。 还公开了一种方法，其包括获得包括电介质材料的插入件，在插入器中形成开口并形成至少部分位于开口内的电容器。

公开(公告)号：US20140141572A1

公开(公告)日：2014-05-22

申请号：US14165855

申请日：2014-01-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chin Hui Chong ,  Hong Wan Ng

IPC: H05K3/30 ,  H05K3/34 ,  H05K3/10

CPC classification number: H05K3/303 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/06156 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H05K3/10 ,  H05K3/34 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

Abstract translation: 下面描述具有多层基板的半导体组件和相关制造方法的各种实施例。 在一个实施例中，用于承载半导体管芯的衬底包括第一路由级别，第二路由级别以及第一和第二路由级别之间的导电通路。 导电通孔具有接近第一路由级的第一端和靠近第二路由级的第二端。 第一路由级别包括端子和导体通孔的端子与第一端之间的第一迹线。 第二路由级别包括导电通孔的第二端和球场之间的第二迹线。 第一路由级别的终端和第二路由级别的球点都可以从基板的同一侧进行电连接。

公开(公告)号：US20130249092A1

公开(公告)日：2013-09-26

申请号：US13893638

申请日：2013-05-14

Applicant: Micron Technology, Inc.

Inventor： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/24 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes positioning a microelectronic device in a cavity of a support member, with the cavity having a closed end with a conductive layer, and an opening through which the cavity is assessable. The microelectronic device can have bond sites, a first surface, and a second surface facing opposite from the first surface. The microelectronic device can be positioned in the cavity so that the second surface faces toward and is carried by the conductive layer. The method can further include electrically coupling the bond sites of the microelectronic device to the conductive layer. In particular embodiments, the microelectronic device can be encapsulated in the cavity without the need for a releasable tape layer to temporarily support the microelectronic device.

Abstract translation: 封装在支撑构件空腔中的微电子器件以及相关方法被公开。 根据一个实施例的方法包括将微电子器件定位在支撑构件的空腔中，其中空腔具有带有导电层的封闭端以及空腔可以评估的开口。 微电子器件可以具有接合位置，第一表面和与第一表面相对的第二表面。 微电子器件可以定位在空腔中，使得第二表面面向导电层并由导电层承载。 该方法还可以包括将微电子器件的键合位置电耦合到导电层。 在具体实施例中，微电子器件可以被封装在空腔中，而不需要可释放的带层来临时支撑微电子器件。

公开(公告)号：US20130235517A1

公开(公告)日：2013-09-12

申请号：US13866713

申请日：2013-04-19

Applicant: MICRON TECHNOLOGY, INC

Inventor： David J. Corisis ,  Choon Kuan Lee ,  Chin Hui Chong

IPC: H05K1/11 ,  G06F1/16 ,  H05K1/18

CPC classification number: H05K1/115 ,  G01R31/026 ,  G06F1/16 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0221 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0296 ,  H05K1/18 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09809 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

公开(公告)号：US20230395569A1

公开(公告)日：2023-12-07

申请号：US18202249

申请日：2023-05-25

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Hari Giduturi ,  Yeon-Chang Hahm

IPC: H01L25/065 ,  H10B80/00 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L2924/1431 ,  H01L23/528 ,  H01L24/08 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2224/08112 ,  H01L2224/0903 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H10B80/00

Abstract: Semiconductor devices, such as memory devices, and associated systems and methods, are disclosed herein. A representative memory device includes a substrate including circuitry, back-end contacts electrically coupled to the circuitry, and front-end contacts. The front-end contacts are configured to receive electrical signals from an external device via a front-end interface. Individual ones of the front-end contacts are electrically coupled to and aligned along an axis with corresponding ones of the back-end contacts.

公开(公告)号：US20230378129A1

公开(公告)日：2023-11-23

申请号：US17750225

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48221 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49177

Abstract: A semiconductor package including a package substrate with an upper surface, a controller, and a die stack. The controller and the die stack are at the upper surface. The die stack includes a shingled sub-stack of semiconductor dies, a reverse-shingled sub-stack of semiconductor dies, and a bridging chip. The bridging chip is bonded between the shingled sub-stack and the reverse-shingled sub-stack, and has an internal trace. A first wire segment is bonded between the controller and a first end of the bridging chip, and a second wire segment is bonded between a second end of the bridging chip and each semiconductor die of the shingled sub-stack. The internal trace electrically couples the first and second wire segments. Additionally, a third wire segment is bonded between the controller and each semiconductor die of the reverse-shingled sub-stack.

公开(公告)号：US20230378128A1

公开(公告)日：2023-11-23

申请号：US17750200

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48221 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49177

Abstract: A semiconductor package having a package substrate including an upper surface, a controller, a first die stack, and a second die stack. The controller, the first die stack, and the second die stack are at the upper surface. The first die stack includes a first shingled sub-stack and a first reverse-shingled sub-stack. The first die stack also includes a first bridging chip between the first shingled and reverse-shingled sub-stacks. The second die stack similarly includes a second shingled sub-stack and a second reverse-shingled sub-stack. The second die stack also includes a second bridging chip bonded to the top of the second reverse-shingled sub-stack. At least a portion of a bottom semiconductor die of the first reverse-shingled sub-stack is vertically aligned with a semiconductor die of the second shingled sub-stack and a semiconductor die of the second reverse-shingled sub-stack.

公开(公告)号：US11710722B2

公开(公告)日：2023-07-25

申请号：US17233129

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Chin Hui Chong ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06572

Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

公开(公告)号：US20230056648A1

公开(公告)日：2023-02-23

申请号：US17982397

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L23/48 ,  H01L27/08 ,  H01L49/02 ,  H01L23/498

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

公开(公告)号：US20230005802A1

公开(公告)日：2023-01-05

申请号：US17843799

申请日：2022-06-17

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Choon Kuan Lee ,  David J. Corisis ,  Chin Hui Chong

IPC: H01L23/18 ,  H01L23/00 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.