公开(公告)号：US20090166857A1

公开(公告)日：2009-07-02

申请号：US11966254

申请日：2007-12-28

申请人： Michael G. Lee

发明人： Michael G. Lee

IPC分类号： H01L23/488 ,  H01L21/58

CPC分类号： H01L25/0657 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/16 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor assembly is provided that includes a first substrate that has a first surface. A second substrate is coupled to and spaced apart from the first substrate. The second substrate has a second surface facing the first surface of the first substrate. The second substrate includes a set of cavities. A set of non-conductive pillars is disposed on and protrudes from the first surface of the first substrate. The set of non-conductive pillars is configured and positioned to engage the set of cavities of the second substrate to align the second substrate with the first substrate.

摘要翻译： 提供一种半导体组件，其包括具有第一表面的第一基板。 第二衬底耦合到第一衬底并与第一衬底间隔开。 第二基板具有面向第一基板的第一表面的第二表面。 第二基板包括一组空腔。 一组非导电柱设置在第一基板的第一表面上并从第一基板的第一表面突出。 该非导电柱组被配置和定位成接合第二衬底的一组空腔以使第二衬底与第一衬底对准。

公开(公告)号：US07504014B2

公开(公告)日：2009-03-17

申请号：US11080195

申请日：2005-03-15

申请人： Michael G. Lee ,  Kishio Yokouchi

发明人： Michael G. Lee ,  Kishio Yokouchi

IPC分类号： C25D5/02

CPC分类号： H01L21/76838 ,  B81C1/0038 ,  B82Y10/00 ,  H01L21/288 ,  H01L51/0048 ,  H05K3/1266 ,  H05K3/249 ,  H05K2201/026 ,  H05K2203/105 ,  H05K2203/135

摘要： The present invention generally relates to circuits on the nanotechnology scale. Specifically, it is directed to methods of fabricating carbon nanotube-based (i.e., CNT-based) circuits. The method involves providing a mixture of carbon nanotubes that is substantially disaggregated and patterning carbon nanotubes through the use of electrostatic forces. Carbon nanotubes in the mixture are typically disaggregated through the introduction of positive charge on the individual nanotubes. The patterning of the carbon nanotubes is typically accomplished using electrostatic attraction between pre-formed metal lines and the charged carbon nanotubes.

摘要翻译： 本发明一般涉及纳米技术规模的电路。 具体地，涉及制造基于碳纳米管（即基于CNT的）电路的方法。 该方法包括提供基本解聚的碳纳米管的混合物，并且通过使用静电力使碳纳米管图案化。 混合物中的碳纳米管通常通过在单个纳米管上引入正电荷来分解。 碳纳米管的图案化通常使用预先形成的金属线和带电的碳纳米管之间的静电吸引来完成。

公开(公告)号：US07403672B2

公开(公告)日：2008-07-22

申请号：US11611255

申请日：2006-12-15

申请人： Dashun Steve Zhou ,  Michael G. Lee ,  Alexei L. Glebov

发明人： Dashun Steve Zhou ,  Michael G. Lee ,  Alexei L. Glebov

IPC分类号： G02B6/00 ,  G02B6/02

CPC分类号： G02B27/283 ,  B29D11/00663 ,  G02F1/0136 ,  G02F1/065

摘要： A method for creating an integrated linear polarizer is provided. An electro-optical component is fabricated and may include a bottom electrode, a bottom cladding layer, side cladding features, an electro-optic polymer layer, a top cladding layer, and a top electrode. After fabrication, the electro-optical component is poled to create or enhance polarization properties of the electro-optic polymer layer. The electro-optical component may be heated to at least a first threshold temperature. An electric field may then be applied to the electro-optical component. In the presence of the electric field, the electro-optical component may be cooled to at or below a second threshold temperature that is less than the first threshold temperature. Once the electro-optical component has cooled to the second threshold temperature, the electric field may be removed.

摘要翻译： 提供一种用于产生集成线性偏振器的方法。 制造电光部件，并且可以包括底电极，底包层，侧包层特征，电光聚合物层，顶包层和顶电极。 在制造之后，电光学部件被极化以产生或增强电光聚合物层的偏振特性。 可以将电光部件加热至至少第一阈值温度。 然后可以将电场施加到电光部件。 在存在电场的情况下，电光部件可以被冷却到等于或低于小于第一阈值温度的第二阈值温度。 一旦电光部件已经冷却到第二阈值温度，则可以去除电场。

公开(公告)号：US07283220B2

公开(公告)日：2007-10-16

申请号：US10808665

申请日：2004-03-24

申请人： Lidu Huang ,  Alexei Glebov ,  Shigenori Aoki ,  Michael G. Lee ,  Kishio Yokouchi

发明人： Lidu Huang ,  Alexei Glebov ,  Shigenori Aoki ,  Michael G. Lee ,  Kishio Yokouchi

IPC分类号： G01N21/41

CPC分类号： G01N21/4133

摘要： Methods and apparatuses for measuring the optical properties of solids, gels, and liquids are disclosed. The apparatuses may be constructed on miniature substrates using conventional semiconductor wafer and packaging processes. The substrates may be mass-produced on wafers, which are then diced to provide individual miniature substrates. High measurement precision, low-manufacturing costs, and other benefits are provided by the present inventions.

摘要翻译： 公开了用于测量固体，凝胶和液体的光学性质的方法和装置。 可以使用传统的半导体晶片和封装工艺在微型基板上构造装置。 衬底可以在晶片上批量生产，然后将其切割以提供单独的微型衬底。 本发明提供了高测量精度，低制造成本和其它益处。

公开(公告)号：US07229219B2

公开(公告)日：2007-06-12

申请号：US10944082

申请日：2004-09-17

申请人： Michael G. Lee ,  Kishio Yokouchi

发明人： Michael G. Lee ,  Kishio Yokouchi

IPC分类号： G02B6/42

CPC分类号： G02B6/4232 ,  G02B6/305

摘要： Disclosed are apparatuses and methods for fast and reliable integration of opto-electric components onto optical routing substrates. Accurate alignment of optical signals to and from the opto-electric components, and short electrical interconnect paths to the components to reduce signal delays to the devices on the components are enabled. In an exemplary embodiment, an attachment area is set out on the optical routing substrate to receive each component. One or more optical waveguides for coupling optical signals with the component are located adjacent to the attachment area. A plurality of conductive pads are located within the attachment area, and are for interconnecting to the component by way of bodies of solder, conductive adhesive, or the like. Interspersed between the conductive pads are a plurality of spacers that set a spacing distance between the attachment area and the opposing surface of the component, resulting in accurate alignment of optical signals.

摘要翻译： 公开了用于将光电组件快速可靠地集成到光路由基板上的装置和方法。 光信号与光电组件的准确对准，以及到组件的短电互连路径，以减少组件上的器件的信号延迟。 在示例性实施例中，在光学布线基板上设置附接区域以接收每个部件。 用于将光信号与该组件耦合的一个或多个光波导位于附接区附近。 多个导电垫位于附接区域内，并且用于通过焊料体，导电粘合剂等与部件互连。 散布在导电焊盘之间的是多个间隔件，其设置附接区域和部件的相对表面之间的间隔距离，导致光信号的精确对准。

公开(公告)号：US06592943B2

公开(公告)日：2003-07-15

申请号：US09757057

申请日：2001-01-08

申请人： Albert W. Chan ,  Michael G. Lee ,  Theresa M. Larson

发明人： Albert W. Chan ,  Michael G. Lee ,  Theresa M. Larson

IPC分类号： B05D132

CPC分类号： H01L23/49883 ,  H01L2924/0002 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2203/0425 ,  Y10T428/24273 ,  H01L2924/00

摘要： A method of depositing solder on a conductive region of a substrate comprising providing a substrate having a substrate aperture and a coefficient of thermal expansion. A polymeric stencil is also provided such as to have a stencil aperture and a coefficient of thermal expansion which is approximately equal to the coefficient of thermal expansion of the substrate. The method also includes disposing the polymeric stencil on the substrate such that the stencil aperture is aligned with a conductive region; and reflowing the solder paste while the polymeric stencil remains disposed on the substrate. The polymeric stencil is then removed from the substrate essentially without any solder-paste being removed with the polymeric stencil. A method of forming a polymeric stencil for solder-paste printing comprising forming in a polymeric sheet of plurality of apertures having wrinkles in the polymeric sheet in proximity to the plurality of apertures, and compressing opposing surfaces of the apertured polymeric sheet toward each other. The compressed apertured polymeric sheet is then heated and rapidly cooled to remove wrinkles in proximity to the apertures. A stencil for use in a fine pitch bumping process comprising a releasable polymeric sheet having a coefficient of thermal expansion of less than about 4.0 ppm/°C. and a structure defining a pair of apertures spaced from each other at a distance less than about 0.20 mm.

摘要翻译： 一种在衬底的导电区域上沉积焊料的方法，包括提供具有衬底孔径和热膨胀系数的衬底。 还提供聚合物模板，例如具有模板孔和热膨胀系数，其大致等于衬底的热膨胀系数。 该方法还包括将聚合物模版设置在基底上，使得模版孔与导电区对齐; 并且当聚合物模板保持设置在基底上时回流焊膏。 然后，聚合物模板基本上从基材上除去，而不用聚合物模板去除任何焊膏。 一种形成用于焊膏印刷的聚合物模板的方法，包括在聚合物片材中具有多个孔隙的多个孔的聚合物片材中形成，并且将多孔聚合物片材的相对表面压向彼此。 然后将压缩的有孔聚合物片材加热并快速冷却以除去孔附近的褶皱。 用于细间距凸起工艺的模版，其包括具有小于约4.0ppm /℃的热膨胀系数的可释放聚合物片材。 以及限定一对彼此以小于约0.20mm的距离彼此隔开的孔的结构。

公开(公告)号：US06543674B2

公开(公告)日：2003-04-08

申请号：US09778658

申请日：2001-02-06

申请人： Michael G. Lee ,  Connie M. Wong ,  Wen-chou Vincent Wang

发明人： Michael G. Lee ,  Connie M. Wong ,  Wen-chou Vincent Wang

IPC分类号： B23K3102

CPC分类号： H01L24/02 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1601 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/043 ,  H05K2203/0475 ,  H05K2203/111 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method for electrically coupling electrode pads comprising forming a reflowed solder bump on a first electrode pad supported by a first substrate. The reflowed solder bump includes a solder material having a solder melting temperature. The method further includes forming a second electrode pad on a second substrate. The second electrode pad has an electrode structure defined by at least one converging continuous arcuate surface terminating in an apex and having an electrode material whose melting temperature is greater than the solder melting temperature of the solder material. The solder bump is heated to reflow or to soften the solder material, and subsequently the apex of the second electrode pad is pressed or inserted into the heated solder bump to couple the first electrode pad to the second electrode pad. A method for solder bump reflow comprising pressing or inserting the apex of an electrode into a reflowed solder bumps, and then reflowing solder material of the reflowed solder bump. A semiconductor assembly including a semiconductor device having an electrode pad coupled to a semiconductor substrate and comprising an electrode structure defined by a pair of arcuate surfaces generally tangentially terminating in an apex.

公开(公告)号：US06518096B2

公开(公告)日：2003-02-11

申请号：US09757005

申请日：2001-01-08

申请人： Albert W. Chan ,  Michael G. Lee

发明人： Albert W. Chan ,  Michael G. Lee

IPC分类号： H01L2144

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13007 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/27013 ,  H01L2224/45124 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3651 ,  H05K3/4614 ,  H05K3/4626 ,  H05K2203/0733 ,  H05K2203/0759 ,  H05K2203/1189 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

摘要： An interconnect assembly and a fluxless method for forming the interconnect assembly. The fluxless method includes providing a first semiconductor substrate having a first pad connected thereto. A post is connected to the first pad and includes a length greater than a thickness of the first pad, and a metallic solder disposed on an associated end of the post. A second semiconductor substrate is provided as having a second pad connected thereto. The fluxless method further includes depositing an unfilled polymeric liquid on the second pad, aligning and contacting the metallic solder with the unfilled polymeric liquid, and forcing by pressure the first and second semiconductor substrate toward each while simultaneously heating the metallic solder and the unfilled polymeric liquid to form a metallurgical joint between the second pad and the metallic solder.

摘要翻译： 用于形成互连组件的互连组件和无助焊剂方法。 无助焊剂方法包括提供具有连接到其上的第一焊盘的第一半导体衬底。 柱连接到第一焊盘并且包括大于第一焊盘的厚度的长度，以及设置在柱的相关联的端部上的金属焊料。 第二半导体衬底被设置为具有连接到其上的第二焊盘。 无助焊剂方法还包括在第二焊盘上沉积未填充的聚合物液体，使金属焊料与未填充的聚合物液体对准和接触，并且通过将第一和第二半导体衬底朝向每个压力迫使金属焊料和未填充的聚合物液体同时加热 以在第二焊盘和金属焊料之间形成冶金接头。

公开(公告)号：US20130026634A1

公开(公告)日：2013-01-31

申请号：US13190761

申请日：2011-07-26

申请人： Michael G. Lee ,  Chihiro Uchibori

发明人： Michael G. Lee ,  Chihiro Uchibori

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/11462 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/01029 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/00014

摘要： In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.

摘要翻译： 在一个实施例中，集成电路（IC）芯片和衬底之间的互连结构包括多种材料。

公开(公告)号：US20120032327A1

公开(公告)日：2012-02-09

申请号：US12852899

申请日：2010-08-09

申请人： Michael G. Lee ,  Chihiro Uchibori

发明人： Michael G. Lee ,  Chihiro Uchibori

IPC分类号： H01L23/488 ,  H01R9/00 ,  H01L21/66

CPC分类号： H01L22/20 ,  H01L22/12 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/131 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17517 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2924/00

摘要： In accordance with some embodiments of the present disclosure, a chip package is provided. The chip package may include a chip, a substrate, and an interconnect layer disposed between the chip and the substrate. In some embodiments, the interconnect layer may include an array of bonding interconnects configured to provide electrical communication between the chip and a printed circuit board and reinforcement interconnects arranged around an outermost row of the array of bonding interconnects.

摘要翻译： 根据本公开的一些实施例，提供了芯片封装。 芯片封装可以包括芯片，衬底和布置在芯片和衬底之间的互连层。 在一些实施例中，互连层可以包括被配置为提供芯片和印刷电路板之间的电连通以及布置在接合互连阵列的最外面行的加强互连的接合互连阵列。